Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Homayoun, Houman; Makhzan, M.A.; Veidenbaum, Alexander V.

doi:10.1145/1450095.1450125

Cited by 15 publications

(5 citation statements)

References 32 publications

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“…When the number of assigned cache ways increases, it costs only wakeup time to switch cache ways back to the active mode from the power-off mode. According to [24], the wakeup time is negligible (i.e., four clock cycles).…”

Section: B Resultsmentioning

confidence: 99%

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache

Kang

Micheli

Lee

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

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Abstract-The advent of 3-D fabrication technology makes it possible to stack a large amount of last-level cache memory onto a multi-core die to reduce off-chip memory accesses and, thus, increases system performance. However, the higher power density (i.e., power dissipation per unit volume) of 3-D integrated circuits (ICs) might incur temperature-related problems in reliability, leakage power, system performance, and cooling cost. In this paper, we propose a runtime solution to maximize the performance (i.e., instruction throughput) of chip-multiprocessors with 3-D stacked last-level cache memory, without thermal-constraint violation. The proposed method combines runtime cache tuning (e.g., cache-way partitioning, cache-way power-gating, cache data placement) with per-core dynamic voltage/frequency scaling (DVFS) in a temperature-aware manner. Experimental results show that the integrated method offers 23% performance improvement on average in terms of instructions per second (IPS) compared with temperature-aware runtime cache tuning only.

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Section: B Resultsmentioning

confidence: 99%

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache

Kang

Micheli

Lee

et al. 2014

Fifteenth International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

show abstract

“…Even on a simple PC, most modern operating systems have and use the option of declaring some critical virtual pages temporarily "unswappable", reducing the amount of physical memory available to user processes. Capacity fluctuations also take place when considering the cache-RAM interface (in which case memory and pages represent, respectively, cache and cache lines): in many multi-core processor designs cache capacity is partitioned dynamically between different cores [9], and low-power chips can often dynamically disable underutilized portions of the cache to save energy [5].…”

Section: Elastic Pagingmentioning

confidence: 99%

Elastic paging

Peserico

2013

Proceedings of the ACM SIGMETRICS/international Conference on Measurement and Modeling of Computer Systems

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We study a generalization of the classic paging problem where memory capacity can vary over time -a property of many modern computing realities, from cloud computing to multi-core and energy-optimized processors. We show that good performance in the "classic" case provides no performance guarantees when memory capacity fluctuates: roughly speaking, moving from static to dynamic capacity can mean the difference between optimality within a factor 2 in space, time and energy, and suboptimality by an arbitrarily large factor. Surprisingly, several classic paging algorithms still perform remarkably well, maintaining that factor 2 optimality even if faced with adversarial capacity fluctuations -without taking those fluctuations into explicit account!

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“…In many multi-core processor designs cache capacity is partitioned dynamically between different cores [24]. And low-power chip designs can often dynamically disable underutilized portions of the cache to save energy [16], again resulting in a capacity that can vary over time.…”

Section: Introductionmentioning

confidence: 99%

Paging with dynamic memory capacity

Peserico

2013

Preprint

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We study a generalization of the classic paging problem that allows the amount of available memory to vary over time -capturing a fundamental property of many modern computing realities, from cloud computing to multi-core and energy-optimized processors. It turns out that good performance in the "classic" case provides no performance guarantees when memory capacity fluctuates: roughly speaking, moving from static to dynamic capacity can mean the difference between optimality within a factor 2 in space and time, and suboptimality by an arbitrarily large factor. More precisely, adopting the competitive analysis framework, we show that some online paging algorithms, despite having an optimal (h, k)−competitive ratio when capacity remains constant, are not (3, k)−competitive for any arbitrarily large k in the presence of minimal capacity fluctuations.In this light it is surprising that several classic paging algorithms perform remarkably well even if memory capacity changes adversarially -even without taking those changes into explicit account! In particular, we prove that LFD still achieves the minimum number of faults, and that several classic online algorithms such as LRU have a "dynamic" (h, k)−competitive ratio that is the best one can achieve without knowledge of future page requests, even if one had perfect knowledge of future capacity fluctuations (an exact characterization of this ratio shows it is almost, albeit not quite, equal to the "classic" ratio k k−h+1 ). In other words, with careful management, knowing/predicting future memory resources appears far less crucial to performance than knowing/predicting future data accesses.

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Multiple sleep mode leakage control for cache peripheral circuits in embedded processors

Cited by 15 publications

References 32 publications

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache

Elastic paging

Paging with dynamic memory capacity

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