Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Shah, Toral; Matrosova, A.; Fujita, Masahiro; Singh, Virendra

doi:10.1007/s10836-018-5703-3

Cited by 9 publications

(6 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The manifestation of a short circuit fault at the output of the LUT node classifies it as checkable if this error is transmitted to the monitored result of calculations, i.e., if the node's LUT output is observable. Otherwise, the error does not reach the result, and this result is considered reliable [19].…”

Section: Improving the Checkability Of Schemes And Trustworthiness Of Resultsmentioning

confidence: 99%

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Drozd¹,

Ruciński²,

Zashcholkin³

et al. 2021

AAIT

View full text Add to dashboard Cite

The article is devoted to the problem of improving FPGA (Field Programmable Gate Array) components developed for safety related systems. FPGA components are improved in the checkability of their circuits and the trustworthiness of the results calculated on them to support fault-tolerant solutions, which are basic in ensuring the functional safety of critical systems. Fault-tolerant solu tions need protection from sources of multiple failures, which include hidden faults. They can be accumulated in significant quanti ties during a long normal operation and disrupt the functionality of fault-tolerant circuits with the onset of the most responsible emer gency mode. Protection against hidden faults is ensured by the checkability of the circuits, which is aimed at the manifestation of faults and therefore must be supported in conjunction with the trustworthiness of the results, taking into account the decrease in trustworthiness in the event of the manifestation of faults. The problem of increasing the checkability of the FPGA component in normal operation and the trustworthiness of the results calculated in the emergency mode is solved by using the natural version re dundancy inherent in the LUT-oriented architecture (Look-Up Table). This redundancy is manifested in the existence of many ver sions of the program code that preserve the functionality of the FPGA component with the same hardware implementation. The checkability of the FPGA component and the trustworthiness of the calculated results are considered taking into account the typical failures of the LUT-oriented architecture. These malfunctions are investigated from the standpoint of the consistency of their mani festation and masking, respectively, in normal and emergency modes on versions of the program code. Malfunctions are identified with bit distortion in the memory of the LUT units. Bits that are only observed in emergency mode are potentially dangerous because they can hide faults in normal mode. Moving potentially dangerous bits to checkable positions, observed in normal mode, is per formed by choosing the appropriate versions of the program code and organizing the operation of the FPGA component on several versions. Experiments carried out with the FPGA component using the example of an iterative array multiplier of binary codes have shown the effectiveness of using the natural version redundancy of the LUT-oriented architecture to solve the problem of hidden faults.

show abstract

Section: Improving the Checkability Of Schemes And Trustworthiness Of Resultsmentioning

confidence: 99%

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Drozd¹,

Ruciński²,

Zashcholkin³

et al. 2021

AAIT

View full text Add to dashboard Cite

show abstract

“…Additionally, the Boolean difference algorithm was used in previous studies [39, 40, 48, 49], and the maximal total number of test vectors is

{2}&amp;#x0005E;n

since all combination of inputs need to be considered. In Shah et al [50, 51], the maximal total number of test vectors is

3m

, where

m

is the number of product terms. Note that

m

is always far greater than

n

in real applications.…”

Section: A Stuck‐at Fault Diagnosis Algorithm For a Gate Network Base...mentioning

confidence: 99%

“…We have performed two experiments to validate the proposed algorithm in this study. The first is an illustration example found in Shah et al [51] to elaborate Algorithm 2. The second experiment addresses the 4‐bit carry look‐ahead adder circuit.…”

Section: Numerical Examplesmentioning

confidence: 99%

Semi‐tensor product‐based algebra‐logic mixed representation and fault diagnosis for a class of gate networks

Liu

Shen

Moschoyiannis

et al. 2023

Asian Journal of Control

View full text Add to dashboard Cite

This article studies an algebra‐logic mixed representation of gate networks and its application to stuck‐at fault diagnosis. First, the gate network is characterized through a logic expression of disjoint sum‐of‐products, and the system structure of the gate network is described based on 2‐to‐1 multiplexers. Then, by resorting to the semi‐tensor product of matrices, a novel algebra‐logic mixed representation is proposed for the gate network through its logic expression and system structure. Furthermore, a novel stuck‐at fault diagnosis algorithm for the gate network is presented, where the stuck‐at fault testability of the gate network is equivalent to the solution existence of the system of linear equations. Finally, the fault diagnosis of the 4‐bit carry look‐ahead adder is carried out to demonstrate the effectiveness and feasibility of the proposed theoretical approach and algorithms.

show abstract

“…ROBDD can be obtained by removing redundancy nodes and isomorphism sub-graphs of Ordered Binary Decision Diagram (OBDD) [13], [14]. Although OBDD can be used as the regular expression of logic circuits, its structure is not necessarily the simplest because OBDD may have redundancy nodes or isomorphism sub-graphs.…”

Section: B Robddmentioning

confidence: 99%

A Novel Logic Detection Algorithm for Logic Circuits

Liu

Zhang

et al. 2019

IEEE Access

View full text Add to dashboard Cite

Synthesizing logic circuits with different logic will result in different circuit structure, and then obtain different circuit performance. However, few studies have focused on logic detection technology that detects which logic is appropriate for the implementation of logic circuits. In this paper, we use Reduced Ordered Binary Decision Diagram (ROBDD) processed by dynamic variable sorting approach to describe logic circuits. Moreover, based on the proposed XOR logic judging condition and logic detection judging condition, we propose a Novel Logic Detection Algorithm (NLDA), which can quickly and effectively detect which logic is appropriate for the implementation of logic circuits. The experimental results on MCNC benchmark circuits show that compared to the logic detection algorithm based on minterms, the logic detection algorithm based on product terms, and the logic detection algorithm based on disjointed cubes, NLDA has the highest logic detection accuracy rate and highest logic detection efficiency.

show abstract

Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Cited by 9 publications

References 17 publications

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Improving Fpga Components of Critical Systemsbased on Natural Version Redundancy

Semi‐tensor product‐based algebra‐logic mixed representation and fault diagnosis for a class of gate networks

A Novel Logic Detection Algorithm for Logic Circuits

Contact Info

Product

Resources

About