Multiplexing Firmware Prototypes for the Global Trigger Subsystem of ATLAS Phase-II Upgrade

Bonini, F.; Begel, M.; Chen, H.; Chen, K.; Liu, H.; Matakias, D.; Tang, Shaochun; Xu, H.; Yin, Weigang; Zhivun, E.

doi:10.1109/tns.2021.3102081

Cited by 1 publication

(1 citation statement)

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“…Each pair of GCM and GRM can be configured as two nodes of MUX, GEP or CTP Interface. The GCM [4] is an Advanced Telecommunications Computing Architecture (ATCA) front board, which contains two big processor Field Programmable Gate Array (FPGA) chips and over 160 multi-gigabit transceivers, used for the major data processing and transmission functions. The GRM is an ATCA rear transition module, which contains one FPGA chip and 82 multi-gigabit transceivers.…”

Section: Introductionmentioning

confidence: 99%

Hardware design of the generic rear transition module for the global trigger system of the ATLAS phase II upgrade

Yin¹,

Tang²,

Bonini³

et al. 2022

J. Inst.

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The High-Luminosity Large Hadron Collider is expected to start operations in the middle of 2027, to deliver more than ten times the integrated luminosity of the Large Hadron Collider Runs 1–3 combined (up to 4000 fb−1). Meeting these requirements poses significant challenges to the hardware design of the trigger and data acquisition system. Global trigger is a new subsystem in the ATLAS phase-II upgrade, which will bring event filter-like capability to the level-0 trigger system. A common hardware platform in Advanced Telecommunications Computing Architecture form factor named Global Common Module is proposed to be configured as processor nodes in the global trigger. To mitigate the risk and simplify the Global Common Module hardware design, a Generic Rear Transition Module is being developed. The Generic Rear Transition Module, which has been implemented with a Xilinx Versal Prime Field Programmable Gate Array and sufficient multi-gigabit transceivers, cannot only achieve system control and communication with the Front-End Link eXchange, but also provide additional processing or readout capacity.

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Section: Introductionmentioning

confidence: 99%