Multiplier Energy Reduction by Dynamic Voltage Variation

Moshnyaga, Vasily G.; Yamanaka, Tatsuhiko

doi:10.1093/ietfec/e88-a.12.3548

Cited by 1 publication

(1 citation statement)

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“…Wei and Yvon [3] proposed a variable precision multiplier which supports variable precisions ranging from 9 to 15 bits and dynamic voltage scaling. Vasily and Tomoyuki [4] proposed a multiplier architecture, which examines k MSBs of the operands to decide whether the entire multiplier is used and accordingly select between two different apply voltages. In the aforementioned multipliers, the reconfigurability function results in: (i) non-negligible silicon area and power overhead; (ii) performance and throughput reduction brought by the shutdown of parts of the circuit and/or use of reduced supply voltage, and (iii) restriction and great margins to the operating condition versatility of the multiplier.…”

Section: Introductionmentioning

confidence: 99%

Dynamic voltage and frequency scaling for low-power multi-precision reconfigurable multiplier

Zhang

Bermak

Boussaid

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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Abstract-In this paper, a 32×32-bit low power multi-precision multiplier is described, in which each building block can be either an independent smaller-precision multiplier or work in parallel to perform higher-precision operations. The proposed multi-precision multiplier enables voltage and frequency scaling for low power operation, while still maintaining full throughput. According to user's arbitrary throughput requirements, the highly dynamic voltage and frequency scaling circuits can autonomously configure the multiplier to operate with the lowest possible voltage and frequency to achieve the lowest power consumption. By carrying out optimizations at the algorithmic and architectural levels, we have completely removed silicon area and power overheads which is always associated with the reconfigurability features. The 32×32-bit low power multiprecision multiplier has been implemented in TSMC 0.18 µm technology. Compared with fixed-width multipliers, the proposed design features around 13.8% and 30% reduction in circuit area and power, respectively. Multi-precision processing featured in this paper accordingly enables voltage and frequency scaling resulting in up to 68% reduction in power consumption.

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Section: Introductionmentioning

confidence: 99%