Multiplier policies for digital signal processing

Ma, G.-K.; Taylor, F.

doi:10.1109/53.45968

Cited by 81 publications

(18 citation statements)

References 14 publications

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“…However, if this property is relaxed, this representation is called the minimal signed digit (MSD) representation, which has as many non-zeros as the CSD representation, but provides multiple representations for a constant [2,3]. Efficient multipliers can be implemented using CSD code and this has been adopted by a number of researchers [4][5][6]. It reduces the number of partial products so as to make multiplication fast and reduces power consumption and area structure of a multiplier for signal processing applications [7].…”

Section: 1mentioning

confidence: 99%

Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology

Saloni¹,

Prakash²

2017

International Journal of Innovative Research in Electrical, Ele

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Designing of low power arithmetic circuit is done considering four levels; algorithm, architecture, circuit and system levels. The most commonly used component of many digital circuit designs is digital multipliers. In order to achieve high data throughput, digital signal processing systems rely on hardware multiplication. There are a number of multipliers available for different applications. This paper focuses on an algorithm, called Canonical Signed Digit Multiplication. This paper presents the performance comparison of the proposed multiplier ie. CSD Multiplier with Array multiplier in terms of power. A Design of 4X4 Multiplier using 90nm Technology is successfully synthesized. Cadence Virtuoso 90nm Technology is used for simulation of the Design. The simulated transient output of 4X4 Multiplier is shown. Multiplier circuit works with 1.8 V power supply. Simulation results obtained show 99.56% reduction in power.

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Section: 1mentioning

confidence: 99%

Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology

Saloni¹,

Prakash²

2017

International Journal of Innovative Research in Electrical, Ele

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“…Due to high speed requirements, parallel array architectures are used for implementing dedicated multipliers in programmable DSP's [4]. The power dissipation of a multiplier depends on the multiplier input values.…”

Section: Measures Of Power Dissipation In the Multipliermentioning

confidence: 99%

Low Power Realization of FIR Filters Using Optimization Techniques

Goyal¹

2012

IOSRJEN

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“…Because FIR filters can always be designed with a sufficient number of bits in the multipliers where truncation or rounding is not required after the multiplication. In the arena of digital FIR filters designing with the constant fixedpoint binary coefficients, significant work has been done (Ma and Taylor, 1990;Lim and Liu, 1988;Dey and Oppenheim, 2008).…”

Section: Introductionmentioning

confidence: 99%

Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

Amin

Mamun²,

Rahman

2011

American Journal of Applied Sciences

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Problem statement: Finite Impulse Response (FIR) filters are widely used in various DSP applications. The design of digital FIR filters is a very basic problem in digital signal processing. A FIR filter with multiple operation capability is certainly very useful for any real-time filtering applications. This article presents a multipurpose FIR filter design modeled by the hardware description language VHDL for real-time filtering application. Approach: The VHDL has its concept of concurrency to cope with the parallelism of digital hardware. The novel feature is the capability of the design to accomplish up to 127variable filter order and an arbitrary filter frequency response. The coefficients are calculated by Hamming windowing technique. Basing on selection embedded in the design, the model is able to execute highpass, lowpass, bandstop and bandpass filtering operations. It is set at 8-bit signed data processing. To filter the input data in time domain, Linear Constant Coefficient Difference Equation (LCCDE) is used by the filter. Results: The design outputs are validated through simulation and compilation. The output results are also compared with the MATLAB implemented calculated output results to test the correctness that proves the effectiveness of the design. Conclusion: With the capability of filtering signal in real time mode utilizing arbitrary filter shape, the multipurpose filter proves to be versatile.

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Multiplier policies for digital signal processing

Cited by 81 publications

References 14 publications

Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology

Low Power 4*4 Canonical Signed Digit Multiplier using 90nm Technology

Low Power Realization of FIR Filters Using Optimization Techniques

Hardware Approach of a Multipurpose Finite Impulse Response Filter for Real-Time Filtering Applications

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