Multiply-add fused RISC architectures for DSP applications

Abstract

Absmct-This paper presents the development of a fixedpoint bit-parallel multiply-add f d (MAF) architecture together with a corresponding V U 1 implementation. The proposed MAF implementation employs the 1.w CMOS technology provided by the Northem Telecom Electronics and available through the Cnnadian Micmdectrpnics Corporation (CMC). This MAF implementation finds a variety of practical applications in high-speed real-time digital signal processing (DSP). The MAF implementation employs a parallel modified Booth multiplier incorporating M array of carry-save adders for the addition 01 the intermediate partial products, and a hardware eifldent carry-skip adder for carry propagation.