Multiprocessor SoC platforms: a component-based design approach

Cesario, W.; Lyonnard, D.; Nicolescu, Gabriela; Paviot, Y.; Yoo, Sungjoo; Jerraya, Ahmed; Gauthier, Lovic; Diaz-Nava, M.

doi:10.1109/mdt.2002.1047744

Cited by 116 publications

(44 citation statements)

References 10 publications

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“…Full surveys [4], [6], [39] described related work. Among the activities in this domain, it is worth recalling: 1) the introduction of new architectures for on-chip networking, such as SPIN [15] and Octagon [20]; 2) the study of encoding schemes for error-resilient communication [8], [9]; 3) various attempts to use packet routing strategies [19], [26], [41]; and 4) efforts to understand the impact of system software and middleware [7], [10].…”

Section: ) On-chip Micronetworkmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2005

IEEE Trans. VLSI Syst.

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Abstract-Systems-on-Chip (SoC) design involves several challenges, stemming from the extreme miniaturization of the physical features and from the large number of devices and wires on a chip. Since most SoCs are used within embedded systems, specific concerns are increasingly related to correct, reliable, and robust operation. We believe that in the future most SoCs will be assembled by using large-scale macro-cells and interconnected by means of on-chip networks. In this paper, we examine some physical properties of on-chip interconnect busses, with the goal of achieving fast, reliable, and low-energy communication. These objectives are reached by dynamically scaling down the voltage swing, while ensuring data integrity-in spite of the decreased signal to noise ratio-by means of encoding and retransmission schemes. In particular, we describe a closed-loop voltage swing controller that samples the error retransmission rate to determine the operational voltage swing. We present a control policy which achieves our goals with minimal complexity; such simplicity is demonstrated by implementing the policy in a synthesizable controller. Such a controller is an embodiment of a self-calibrating circuit that compensates for significant manufacturing parameter deviations and environmental variations. Experimental results show that energy savings amount up to 42%, while at the same time meeting performance requirements.Index Terms-Electrical parameter variations, interconnect for networks-on-chip, low-power systems-on-chip (SoC), self-calibrating designs, VLSI design methodology.

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Section: ) On-chip Micronetworkmentioning

confidence: 99%

A robust self-calibrating transmission scheme for on-chip networks

Worm

Ienne

Thiran

et al. 2005

IEEE Trans. VLSI Syst.

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“…HW/SW-codesign methods [13], [14] provide a fluid transition from software to hardware implementation. They focus on interface design and system verification.…”

Section: Hardware-based Design Analysismentioning

confidence: 99%

Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding

Seitner

Bleyer

Gelautz

et al. 2009

IEEE Trans. Circuits Syst. Video Technol.

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Abstract-In this paper, we introduce a high-level simulation methodology for the modeling of multicore video processing architectures. This method allows design space explorations of parallel video processing applications (VPAs). It is used to test the performance of running a VPA on arbitrary virtual hardware and software configurations. The method represents an alternative to performing a "complete" decoder implementation on a field-programmable gate array or an applicationspecific integrated circuit. The use of our method, therefore, yields the advantage of being considerably more time, labor, and cost efficient. As an application, we use our method for designing a parallel H.264 decoder targeting 720p25 resolution at bit-rates up to 50 Mb/s. Starting from a single-core decoder implementation, we use our simulator for estimating the performance gain when using a multicore architecture. We then detect the major performance bottlenecks in this multicore system and perform additional decoder splittings accordingly until we reach the targeted requirements. The use of functional splitting (i.e., pipelining) and data-parallel processing is demonstrated. The final H.264 decoder architecture is capable of fulfilling our performance requirements.Index Terms-Design exploration, H.264 decoder, parallel architectures, video processing.

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“…Several approaches deal with automatic generation and synthesis of communication [5], [6]. None of these, however, provides intermediate models that break the design task into smaller steps required for early exploration.…”

Section: Related Workmentioning

confidence: 99%

“…Note that, while communication over each link (PE1 to CE1 and CE1 to PE2) is now synchronous, the overall transfer from PE1 to PE2 may be asynchronous due to buffering in CE1. 5 In the TLM [ Fig. 9(c)], each bus in the network is now represented with one TLM and a set of interrupt channels (e.g., Bus1 and Int1).…”

Section: Communication Channelsmentioning

confidence: 99%

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

Gerstlauer¹,

Shin²,

Peng³

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components. To this end, corresponding communication design flows that are supported by efficient design automation techniques need to be developed. In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures. Our approach supports a two-stage design flow using automated model refinement toward custom heterogeneous communication networks. Starting from an abstract specification of the desired communication channels, our environment automatically generates tailored network models at various levels of abstraction. At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Our experimental results show significant productivity gains over a traditional communication design, allowing early and rapid design space exploration.Index Terms-Communication synthesis, embedded systems, heterogeneous multiprocessor system-on-chip (MPSoC), systemlevel design, transaction-level modeling (TLM).

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Multiprocessor SoC platforms: a component-based design approach

Cited by 116 publications

References 10 publications

A robust self-calibrating transmission scheme for on-chip networks

A robust self-calibrating transmission scheme for on-chip networks

Development of a High-Level Simulation Approach and Its Application to Multicore Video Decoding

Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

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