Multiprocessor Task Migration Implementation in a Reconfigurable Platform

Gantel, Laurent; Layouni, Salah; Benkhelifa, Mohamed El Amine; Verdier, François; Chauvet, S.

doi:10.1109/reconfig.2009.37

Cited by 15 publications

(4 citation statements)

References 6 publications

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“…Activating/freeing up a core boils down to activating/deactivating a preloaded code instance since the sensordata processing is performed independently in each core. This also implies that this mechanism has no context switch overhead and has a negligible reconfiguration overhead [6].…”

Section: Implementation Architecture For Rpcmentioning

confidence: 95%

“…(ii) The shared memory needs to store γ M C old input signals. The other important ingredient is the reconfiguration mechanism, which realizes switching between the configurations at runtime using techniques proposed in [6]. In this method, control codes for the sensor-to-actuation loop are already loaded on γ M C cores.…”

Section: Implementation Architecture For Rpcmentioning

confidence: 99%

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Reconfigurable Pipelined Control Systems

Sánchez¹,

Nikkhah

Goswami

et al. 2021

IEEE Des. Test

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Section: Implementation Architecture For Rpcmentioning

confidence: 95%

Section: Implementation Architecture For Rpcmentioning

confidence: 99%

Reconfigurable Pipelined Control Systems

Sánchez¹,

Nikkhah

Goswami

et al. 2021

IEEE Des. Test

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“…al [14] migrate tasks between heterogeneous cores of an MPSoC on top of µC/OS-II. Migration requests are pending until the execution has reached a user-defined checkpoint.…”

Section: Manual Definitionmentioning

confidence: 99%

Migration-aware WCET estimation for heterogeneous multi-cores

Munk

Richling

2014

SIGBED Rev.

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Heterogeneous Multi-Processor Systems-on-Chip (MPSoCs) are increasingly used in the embedded safety-critical domain with real-time constraints. Fault tolerance, temperature distribution, and energy management in such systems can be improved by reconfiguration mechanisms that rely on task migration. In order to serve a migration request while meeting all deadlines, the remaining worst-case execution time (WCET) must be known as tightly bound as possible. We show that scaling the WCET by a linear factor to compensate for migration between heterogeneous cores can lead to dangerous underestimations. Our approach is to split the WCET of a task into parts and derive the WCET for all parts on all individual core architectures. We present a formal model to show how the remaining WCET can be calculated as the sum of unprocessed parts. We differentiate between two levels of heterogeneity, namely same instruction set architecture (ISA) with different performance characteristics and different ISAs. We propose three implementation concepts to partition a task, calculate the remaining WCET, and perform the migration.

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“…Muneeswari [39] proposed a technique in which critical and non-critical tasks are classified, where the critical tasks are scheduled, such that re-utilization of the cache is minimized while, for non-critical tasks, round robin scheduling is used. Holmbacka et al and Gantel et al [40,41] proposed a task replication mechanism in which tasks are migrated between different cores. When a task is created on one core, a replica of the same task is created on other available cores.…”

Section: Introductionmentioning

confidence: 99%

Affinity-Based Task Scheduling on Heterogeneous Multicore Systems Using CBS and QBICTM

et al. 2021

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This work presents the grouping of dependent tasks into a cluster using the Bayesian analysis model to solve the affinity scheduling problem in heterogeneous multicore systems. The non-affinity scheduling of tasks has a negative impact as the overall execution time for the tasks increases. Furthermore, non-affinity-based scheduling also limits the potential for data reuse in the caches so it becomes necessary to bring the same data into the caches multiple times. In heterogeneous multicore systems, it is essential to address the load balancing problem as all cores are operating at varying frequencies. We propose two techniques to solve the load balancing issue, one being designated “chunk-based scheduler” (CBS) which is applied to the heterogeneous systems while the other system is “quantum-based intra-core task migration” (QBICTM) where each task is given a fair and equal chance to run on the fastest core. Results show 30–55% improvement in the average execution time of the tasks by applying our CBS or QBICTM scheduler compare to other traditional schedulers when compared using the same operating system.

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Multiprocessor Task Migration Implementation in a Reconfigurable Platform

Cited by 15 publications

References 6 publications

Reconfigurable Pipelined Control Systems

Reconfigurable Pipelined Control Systems

Migration-aware WCET estimation for heterogeneous multi-cores

Affinity-Based Task Scheduling on Heterogeneous Multicore Systems Using CBS and QBICTM

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