Multistate Memory Enabled by Interface Engineering Based on Multilayer Tungsten Diselenide

Abstract

The diversification of data types and the explosive increase of data size in the information era continuously required to miniaturize the memory devices with high data storage capability. Atomically thin two-dimensional (2D) transition metal dichalcogenides (TMDs) are promising candidates for flexible and transparent electronic and optoelectronic devices with high integration density. Multistate memory devices based on TMDs could possess high data storage capability with a large integration density and thus exhibit great potential applications in the field of data storage. Here, we report the multistate data storage based on multilayer tungsten diselenide (WSe2) transistors by interface engineering. The multiple resistance states of the WSe2 transistors are achieved by applying different gate voltage pulses, and the switching ratio of the memory can be as large as 105 with high cycling endurance. The water and oxygen molecules (H2O/O2) trapped at the interface between the SiO2 substrate and WSe2 introduce the trap states and thus the large hysteresis of the transfer curves, which leads to the multistate data storage. In addition, the laminated Au thin film electrodes make the contact interface between the electrodes and WSe2 free of dangling bond and Fermi level pinning, thus giving rise to the excellent performance of memory devices. Importantly, the interface trap states can be easily controlled by a simple oxygen plasma treatment of the SiO2 substrate, and subsequently, the performance of the multistate memory devices can be manipulated. Our findings provide a simple and efficient strategy to engineer the interface states for the multistate data storage applications and would motivate more investigations on the trap state-associated applications.

Nonvolatile electrical switching of optical and valleytronic properties of interlayer excitons

“…S1) . The substrate was oxygen-plasma cleaned for 10 min before the dry-transfer procedure, so as to make a uniform hydrophilic surface 14 .

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“…S8 ), further supporting the chemical-doping mechanism. Additionally, the area of the hysteresis curve is in proportion to the chemical-doping level, and could be quantitatively controlled by oxygen-plasma-cleaning time of the SiO 2 /Si substrate as demonstrated in WSe 2 -based memories 14 . The hysteretic behavior is re-confirmed by two-cycle-scanning measurements (Fig.…”

Current Tunneling Characterization of Oxidized Black Phosphorus by Graphite Thin Film Electrodes

“…1(d). This two-dimensional material stacking process was performed using a micro-transferring system with polydimethylsiloxane (PDMS) stamping [14,19,20]. The TG and the BG were then contacted using Cr/Au (10 nm / 100 nm) electrodes via normal e-beam lithography [see Fig.…”

“…The current tunneling characterization of this oxidized BP layer was investigated by using graphene-electrodes sandwiched heterostructures. Because oxides can be applied to memory devices [15][16][17][18][19], the electrical characterization of an oxidized BP layer will make a good reference for atomically thin memory device applications.…”

Multiposition Controllable Gate WS2/MoS2 Heterojunction Phototransistor and Its Applications in Optoelectronic Logic Operation and Emulation of Neurotransmission

“…provide a feasible platform for construction of electronic and optoelectronic devices with excellent characteristics and novel functions, such as metal-oxide-semiconductor field-effect transistors, [3][4][5] junction field-effect transistors, [6][7][8] photodetectors, [9][10][11] and memory devices. [12][13][14][15] Moreover, various logic gates, such as inverter, NAND, NOR, and XOR gates, have been recently proposed. [16][17][18][19][20] Logic half-adder circuits, parity-checker circuits, and microprocessors based on TMDC devices have already been implemented.…”