Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review

Abstract

| Memristive devices have the potential for a complete renewal of the electron devices landscape, including memory, logic, and sensing applications. This is especially true when considering that the memristive functionality is not limited to two-terminal devices, whose practical realization has been demonstrated within a broad range of different technologies. For electron devices, the memristive functionality can be generally attributed to a material state modification, whose dynamics can be engineered to target a specific application. In this review paper, we show that trap charging dynamics can explain some of the memristive effects previously reported for Schottky-barrier field-effect Si nanowire transistors (SB SiNW FETs). Moreover, the SB SiNW FETs do show additional memristive functionality due to trap charging at the metal/ semiconductor surface. The combination of these two memristive effects into multiterminal metal-oxide-semiconductor field-effect transistor (MOSFET) devices gives rise to new opportunities for both memory and logic applications as well as new sensors based on the physical mechanism that originate memristance. In the special case of four-terminal memristive Si nanowire devices, which are presented for the first time in this paper, enhanced functionality is demonstrated. Finally, the multiterminal memristive devices presented here have the potential of a very high integration density, and they are suitable for hybrid complementary metal-oxide-semiconductor (CMOS) cofabrication with a CMOS-compatible process.

Designing Strained Interface Heterostructures for Memristive Devices

“…In the last few years the field of ionic memristive memories (also often referred to as memristors or resistive switches) rapidly emerged and received considerable attention due to their potential to replace electronic transistor based technology in future memory and computing architectures. [14][15][16][17][18] This is because ionic memristive devices offer lower power consumption, shorter read/write times, superior endurance, etc. compared to conventional technologies.…”

Fabrication of a W/CuxO/Cu memristor with sub-micron holes for passive sensing of oxygen

“…9(a), oxygen is first ionically adsorbed (O 2 = O 2-+ h+) onto the surface from the surrounding environment [10], [13]. We can write the change in oxygen concentration C with time across a thin region of thickness dx at a depth x from the Cu x O surface as the difference between the flux F of oxygen per unit area entering the region and that leaving the region [20] (2) A Taylor-series expansion then allows us to approximate the last term as (3) which allows us to rewrite the change in oxygen concentration as (4) Fick's first law states that the flux density is proportional to the concentration gradient, where D is the diffusivity: (5) Combining (4) and (5), we obtain Fick's second law (6) which states that diffusion causes the concentration in the layer to change with time. In our case, it is the diffusion of ionically adsorbed oxygen that causes the oxygen concentration in the Cu x O layer to increase with time.…”

“…Depending on the bias voltage applied, these devices can switch between low and high resistance states that are hundreds to thousands of ohms and tens to thousands of kilo-ohms, respectively. Understanding of this phenomenon combined with the increasing limits of complementary metal-oxide semiconductors [1, 2,6] have led to a surge in memristor research for memory applications, particularly in non-volatile memory (NVM) devices, or resistive random access memories (RRAMs) [6,7]. Considerable attention has also been given to the memristor's application for logic, including as synapses in neuromorphic systems [8]- [10].…”

Research progresses of resistive random access memory

“…流<1 nA的特性 [249] . 很好的应用潜力 [258][259][260] . 另外, 阻态连续可调的阻变存 储器(也称为忆阻器)也具有类似神经突触的可塑性, 因此忆阻器及其集成阵列在并行处理、类脑计算等方 图 15 (网络版彩图) (a)-(d) 4层堆叠三维RRAM垂直交叉 阵列的加工工艺流程; (e)-(g) 加工工艺中相应的在线检测 结果; (h) 4层3D V-RRAM阵列的结构示意图; (i) 4层8×32 3D V-RRAM阵列的光学照片 [249] Figure 15 (Color online) (a)-(d) The process flow of 3D integration of V-RRAM on 8 inch wafer; (e)-(g) the inline check at each step of process flow; (h) the schematic of 4 layer 3D V-RRAM array; (i) the optical image of 4 layer 8×32 3D V-RRAM array [249] .…”