Multithread execution mechanisms on RICA-1 for massively parallel computation

Okamato, K.; Sakai, Shuichi; Matsuoka, Hiroshi; Yokota, Takashi; Hirono, Hideo

doi:10.1109/pact.1996.552653

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Cited by 4 publications

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“…Multithreaded architectures have the potential to address this latency problem by supporting multiple flows of control (threads) on a multithreaded processor. Through fast switching among threads, multithreaded architectures can tolerate a variety of latencies, such as those caused by branch instructions, memory accesses, and interprocessor communication and synchronization [4,30,12,3,10,24,21,33,49,31]. As long as there is enough parallelism in an application, a multithreaded architecture can hide these latencies and utilize available communication bandwidth effectively.…”

Section: Introductionmentioning

confidence: 99%