MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

Yan, Aibin; Li, Zhixing; Gao, Zhongyu; Zhang, Jing; Huang, Zhengfeng; Ni, Tianming; Cui, Jie; Wang, Xiaolei; Girard, Patrick; Wen, Xiaoqing

doi:10.1109/tcad.2024.3357593

Cited by 34 publications

(4 citation statements)

References 26 publications

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“…The high chirality offers a low V th hence low delay as the delay negative exponential dependence with the V th of a transistor. The write delay which gives an account of the time needed to change the storage node after the WL is ON and is determined by the time instant WL reaches 50% of its value and node Q rises to 90% or falls to 10% of its final value [64].…”

Section: Write Operation Of the Proposed Tsram Cellmentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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In this paper, a carbon nanotube field-effect transistor (CNTFET) based low power and robust ternary SRAM (TSRAM) cell with enhanced static noise margin (SNM) has been proposed. The proposed cell uses a low-power cell core and a stack of 2 CNTFETs to discharge the read bit line (RBL) to ground, unlike the previous SRAM designs which use read buffers or transmission gates (TG) to alter the voltage levels on the RBL. The proposed TSRAM cell has been simulated relentlessly, using the Stanford 32 nm CNTFET technology mode file with Synopsis HSPICE tool under various operating conditions. Unlike other designs, the cross-coupled ternary inverters used as the cell core in the proposed TSRAM show higher gain and steep curves in the transition region mitigating the static power of the cell. The simulation results exhibit improvements in performance parameters like power consumption, energy, noise margins, and reliability. At 0.9 V supply voltage, the proposed TSRAM cell offers 52.44% and 43.17% reduction in write and read static power, a PDP reduction of 35.29% in comparison, and a 36.36% improvement in SNM compared to best designs under investigation. Also, the proposed TSRAM design shows higher robustness compared to other designs.

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Section: Write Operation Of the Proposed Tsram Cellmentioning

confidence: 99%

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

View full text Add to dashboard Cite

show abstract

“…Nowadays, in the dual-purpose planning of the microgrid, to reduce both the pollution and the cost of power supply, the effect of variable speed water pumps is considered. The presence of such pumps in the water distribution network has created an important connection between the water and power networks [ 21 , 22 ]. Therefore, the water distribution system is an important electricity consumer and its lack of supply can cause a decrease in water load.…”

Section: Introductionmentioning

confidence: 99%

Designing a multi-objective energy management system in multiple interconnected water and power microgrids based on the MOPSO algorithm

Alkuhayli,

Dashtdar,

Flah

et al. 2024

Heliyon

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“…While both binary and quaternary conversions involve repeated division, the key difference lies in the divisor: binary uses repeated division by 2, while quaternary uses repeated division by 4. The counting sequence in quaternary is: 0, 1, 2, 3,10,11,12,13,20,21,22,23,30,31,32,33,100,101, and so on. Storing a number in quaternary requires significantly fewer bits compared to binary.…”

Section: Introductionmentioning

confidence: 99%

“…The power consumed in interconnects is the dynamic power due to the switching of interconnect capacitances. It has been reported that interconnect power is 50% of the dynamic power in a high-performance microprocessor [10]. So the computational capability of quaternary circuits in terms of data handling capability, lower interconnects, reduced interconnects and lower power consumption outreaches that in binary circuits.…”

Section: Introductionmentioning

confidence: 99%

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

Haq,

Abbasian,

Khurshid

et al. 2024

Phys. Scr.

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Multi-valued logic (MVL), which is an extension of binary logic, is a framework for representing complex systems with more than two truth values. This paper delves into the circuit design, computational aspects, and practical applications of the quaternary logic system, which is a type of MVL with four truth values. The multi-threshold property of carbon nanotube field-effect-transistors (CNTFET), along with resistive random-access memory (RRAM) having the capability of storing multiple resistance values, has been used in the design of quaternary logic gates and arithmetic circuits. The non-volatility in the design achieved using RRAMs enables the circuits to be used in reconfigurable logic and in-memory computational applications. The properties of RRAM, like resistance switching and multi-cell storage, have been used to optimize the proposed circuits. Quaternary logic gates such as inverter, NAND, and NOR, and quaternary arithmetic circuits including decoder, half adder, and multiplier have been designed. The power-delay-product (PDP) of the proposed quaternary inverter, NAND, NOR, half adder, and multiplier is 62.38%, 93.4%, 80.29%, 14.79%, and 20% less than the least PDP of the quaternary designs under consideration, respectively.

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MURLAV: A Multiple-Node-Upset Recovery Latch and Algorithm-Based Verification Method

Cited by 34 publications

References 26 publications

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Low-power and robust ternary SRAM cell with improved noise margin in CNTFET technology

Designing a multi-objective energy management system in multiple interconnected water and power microgrids based on the MOPSO algorithm

Energy-efficient design of quaternary logic gates and arithmetic circuits using hybrid CNTFET-RRAM technology

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