Mutual-Information Optimized Quantization for LDPC Decoding of Accurately Modeled Flash Data

Wang, Jiadong; Dong, Guiqiang; Zhang, Tong; Wesel, Richard

doi:10.48550/arxiv.1202.1325

Cited by 1 publication

(1 citation statement)

References 13 publications

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“…In Figure 9, the whole range is separated into 3 quantized regions, hence this quantization model is equivalent to a 2-input, 3-output channel model with X ∈ {0, 1} and Y ∈ {0, e, 1} given in Figure 10, which is similar to the model of single-level cell (SLC) NAND flash memory with 2 reads in [24].…”

Section: Boundaries Defined By Stepwise Mutual Informationmentioning

confidence: 99%

Polar-coded forward error correction for MLC NAND flash memory

Song

Zeng

et al. 2018

Sci. China Inf. Sci.

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With the ever-growing storage density, high-speed, and low-cost data access, flash memory has inevitably become popular. Multi-level cell (MLC) NAND flash memory, which can well balance the data density and memory stability, has occupied the largest market share of flash memory. With the aggressive memory scaling, however, the reliability decays sharply owing to multiple interferences. Therefore, the control system should be embedded with a suitable error correction code (ECC) to guarantee the data integrity and accuracy. We proposed the pre-check scheme which is a multi-strategy polar code scheme to strike a balance between reasonable frame error rate (FER) and decoding latency. Three decoders namely binaryinput, quantized-soft, and pure-soft decoders are embedded in this scheme. Since the calculation of soft loglikelihood ratio (LLR) inputs needs multiple sensing operations and optional quantization boundaries, a 2-bit quantized hard-decision decoder is proposed to outperform the hard-decoded LDPC bit-flipping decoder with fewer sensing operations. We notice that polar codes have much lower computational complexity compared to LDPC codes. The stepwise maximum mutual information (SMMI) scheme is also proposed to obtain overlapped boundaries without exhausting search. The mapping scheme using Gray code is employed and proved to achieve better raw error performance compared to other alternatives. Hardware architectures are also given in this paper. Song H, et al. Sci China Inf Sci 2 Challenges and motivationAs the required storage density increases, most NAND flashes consider to store 4 bits in a single cell [5][6][7][8], which results in worse raw error performance. Therefore, powerful forward-error correction (FEC) methods are required, and voluminous researches on conventional error correction code (ECC) schemes for NAND flash memory emerge [9][10][11][12][13]. Recently, low-density parity-check (LDPC) codes have been considered. To balance performance and complexity, hybrid scheme combining hard decoder and soft decoder is always employed. However, the accepted soft decoders such as min-sum and belief-propagation (BP) suffer from high complexity. Identifying an alternative code might serve as a solution.Recently, polar codes [14] have shown capacity-achieving performance and reasonable complexity [15,16]. Besides its good performance over binary-input discrete memoryless channels (B-DMCs), N -bit polar code's encoding and decoding complexity is as low as O(N log N ), which is much lower than that of LDPC code. Consequently, polar codes have been selected as the control channel code for the enhanced mobile broadband (eMBB) scenario by 3GPP [17]. Inspired by few existing literature [18], this paper devotes itself in proposing an efficient polar-coded forward error correction for multi-level cell (MLC) NAND flash memory.

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Section: Boundaries Defined By Stepwise Mutual Informationmentioning

confidence: 99%