MVP: a mutation-based validation paradigm

Abstract

Abstract-We present a Mutation-based Validation Paradigm (MVP) technology that can handle complete high-level microprocessor implementations and is based on explicit design error modeling, design error simulation, and model-directed test vector generation. We first present a control-based coverage measure that is aimed at exposing design errors that incorrectly set control signal values. We then describe MVP's high-level concurrent design error simulator that can handle various modeled design errors. We then present fundamental techniques and data structures for analyzing high-level circuit implementations and present various optimizations to speed-up the processing of data structures and consequently speed up MVP's overall test generation process. We next introduce a new automatic test vector generation technique for high-level hardware descriptions that generates a test sequence by efficiently solving constraints on multiple finite state machines. To speed up the test generation, MVP is empowered by learning abilities via profiling various aspects of the test generation process. Our experimental results show that MVP's learning abilities and automated test vector generation effectiveness make MVP significantly better than random or pseudorandom validation techniques. IndexTerms-Simulation-based design verification, concurrent design error simulation, high-level deterministic test generation, design error modeling. I. INTRODUCTIONigital circuit design methodologies have reached a highly optimized state, but the circuit validation methods used in industry are still subjective to the validation engineer on the job. Many circuit validation methods for high-level hardware descriptions are available and are in competition with oneanother and most of these methods do not provide a standalone solution. As a result, circuit validation is still an art mastered by an engineer through experience and observations, as opposed to a systematic technique that can be easily disseminated. These validation engineers develop an intuition on how to perform circuit validation, and most importantly, on how much circuit validation is necessary. It is therefore Manuscript received September 23, 2006; revised July 16, 2007. possible to reduce the time and money required to create circuits by reducing the human effort required in circuit validation through a systematic and easily-reproducible system comprised of software tools and deterministic practices, both in software and human effort."Black-box" circuit validation is a strategy that does not require the validation system to have prior inside knowledge of the circuit under validation. It currently relies on random or pseudo-random test patterns to validate the "black box" because such a validation system has no way of efficiently deciphering how to generate the most effective instruction sequence for circuit validation.Current industry standard practices rely on random and pseudo-random instruction sequence generation techniques that bet on the statistical nature of their practices...

Simulation Data Mining for Functional Test Pattern Justification

“…In our previous research [1][5] [6], we have developed the methods that implement MVP (Mutationbased Validation Paradigm), our validation environment for high-level microprocessor implementations. MVP is able to handle complete implementations because it only uses high-level information, and only uses the hardware description language (HDL) information relevant to the set of constraints when identifying all relevant architectural states.…”

“…For our validation paradigm [6], we have created the notion of a prospect state to define an architectural state in terms of a set of constraints. For each constraint, there is a data dependency of its corresponding signal to the set of primary inputs and internal registers, and there is a set of control requirements that allow that data dependency to become active.…”