N-polar GaN HEMT with Al<sub>2</sub>O<sub>3</sub>gate insulator

Hayasaka, A.; Aonuma, Ryosuke; Hotta, Koushi; Makabe, Isao; Yoshida, Shigeo; Miyamoto, Yasuyuki

doi:10.1109/iciprm.2019.8819128

Cited by 1 publication

(1 citation statement)

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“…6,7) In addition, there is a potential to achieve lower ohmic resistance by means of direct contact between the GaN channel and ohmic electrodes. 8) Several groups have reported N-polar HEMTs, [7][8][9][10][11][12][13][14][15][16][17][18][19][20] which includes some recent outstanding high-frequency performance at 30 GHz 9,18) and 94 GHz, 9,17,19,20) and high-power performance with a breakdown voltage of over 2000 V. 12) A grand challenge in N-polar GaN HEMTs is to achieve a stable MIS (metal-insulator-semiconductor) gate structure because Schottky gates often suffer from a large gate leakage current. Choice of the gate stack, its deposition process, surface treatments, and the post-deposition process should be optimized for this purpose.…”

Section: Introductionmentioning

confidence: 99%

Reverse bias annealing effects in N-polar GaN/AlGaN metal-insulator-semiconductor high electron mobility transistors

Prasertsuk¹,

Suemitsu²,

Matsuoka³

2021

Jpn. J. Appl. Phys.

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Reverse bias annealing (RBA) is applied to N-polar GaN high electron mobility transistors (HEMTs) to improve the quality of the gate stack interface. As demonstrated for Ga-polar HEMTs, RBA improves the stability of the gate stack interface. However, the decrease in the maximum drain current density is observed as a unique phenomenon for the N-polar HEMTs. The calculation of the band profile suggests that in the N-polar HEMTs the electrons injected from the gate electrode by the reverse bias accumulate at the gate stack interface in the extrinsic gate region. This promotes the electron trapping in the gate stack, which results in an increase in the source access resistance by the virtual gate phenomenon. In the Ga-polar HEMTs, the electrons tend to accumulate at the AlGaN/GaN interface rather than the gate stack interface, which gives less chance of the virtual gate phenomenon.

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