2003
DOI: 10.1149/1.1539502
|View full text |Cite
|
Sign up to set email alerts
|

N-Type Dopant Activation Behaviors in Poly Si[sub 1−x]Ge[sub x] Films with Ge Contents and Activation Temperatures

Abstract: We investigated the electrical properties and microstructures of n-type doped poly Si 1Ϫx Ge x films with Ge contents using hall measurement, four-point probe, transmission electron microscopy, and energy dispersive X-ray spectrometry to apply to gate electrode of complementary metal oxide semiconductor field effect transistor. The sheet resistance of poly Si 1Ϫx Ge x films implanted with arsenic decreased with the decrease of Ge content and the increase of activation temperature due to the increase of carrier… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
2
0

Year Published

2005
2005
2005
2005

Publication Types

Select...
2

Relationship

0
2

Authors

Journals

citations
Cited by 2 publications
(2 citation statements)
references
References 17 publications
0
2
0
Order By: Relevance
“…9,10 PDE decreases with the percentage of Ge in p-type MOS ͑PMOS͒, but achieves a minimum in n-type MOS ͑NMOS͒ when x Ͻ 0.2 with poly-SiGe films deposited on Si seeds, which is because the solubility of NMOS dopants ͑e.g., As͒ decreases with higher amounts of Ge. 11 To enable practical manufacturing of deep submicrometer, poly-SiGe gate electrode based CMOS transistors, however, other related technologies that are essential to the fabrication of such devices must be developed. Examples of such technologies include etching process to form the gate profiles reproducibly, resist stripping process that would avoid eroding the gate profile, and, most fundamentally, the ability to deposit reproducibly and efficiently thin and uniform poly-SiGe films ͑e.g., 20-100 nm͒ over large areas ͑e.g., 200 mm diameter Si wafers͒.…”
mentioning
confidence: 99%
“…9,10 PDE decreases with the percentage of Ge in p-type MOS ͑PMOS͒, but achieves a minimum in n-type MOS ͑NMOS͒ when x Ͻ 0.2 with poly-SiGe films deposited on Si seeds, which is because the solubility of NMOS dopants ͑e.g., As͒ decreases with higher amounts of Ge. 11 To enable practical manufacturing of deep submicrometer, poly-SiGe gate electrode based CMOS transistors, however, other related technologies that are essential to the fabrication of such devices must be developed. Examples of such technologies include etching process to form the gate profiles reproducibly, resist stripping process that would avoid eroding the gate profile, and, most fundamentally, the ability to deposit reproducibly and efficiently thin and uniform poly-SiGe films ͑e.g., 20-100 nm͒ over large areas ͑e.g., 200 mm diameter Si wafers͒.…”
mentioning
confidence: 99%
“…The deposition techniques and physical and electrical properties of the poly-SiGe films have been broadly investigated, and the gate depletion reduction properties of Si 1Ϫx Ge x electrodes have been demonstrated in capacitors and long-channel CMOS transistors in literature. [13][14][15][16][17][18][19][20] However, the use of poly-SiGe as the gate electrode has serious implications on process technologies such as plasma dry etching, resist ashing, wafer cleaning, and oxidation that are essential steps for transistor fabrication. The conventional process technologies used for the poly-Si gate electrode significantly impact the poly-SiGe gate electrode profile and thus, the critical dimension ͑CD͒.…”
mentioning
confidence: 99%