Nano‐CMOS Design for Manufacturabililty

Wong, Ban P.; Zach, Franz X.; Moroz, Victor; Mittal, Anurag; Starr, Greg; Kahng, Andrew B.

doi:10.1002/9780470382820

Cited by 19 publications

(16 citation statements)

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“…In fact, considering the 3-sigma delay value as a timing constraint, it is statistically assured that about 99.87% of the fabricated circuits satisfy the target speed [1]. As the main effect of the intra-die PVs, all the curves are shifted up with respect to those drawn in Figure 1.…”

Section: Impact Of Intra-die Process Variability For Different Power mentioning

confidence: 69%

“…Under process variations, the delay of a given circuit can be modeled by a normal distribution with a probability density function (PDF) characterized by the mean and the standard deviation values [1]. By analyzing the PDF of the delay for a given energy constraint, useful information about the achievable timing yield can be obtained.…”

Section: Timing Yield Issues and Design Guidelines For Energy-aware Amentioning

confidence: 99%

“…The ratio between the maximum spread 3σ and the mean value µ (i.e., 3σ/µ [1]) was considered as a measure of the uncertainty of the delay. As can be easily observed in Figure 6, during the optimization for power savings (i.e., VDD lower than the nominal value) the delay variability increases at a rate similar to the decreasing of the nominal delay, and hence timing yield worsens during this optimization.…”

Section: Impact Of Intra-die Process Variability For Different Power mentioning

confidence: 99%

“…This potentially impacts the parametric yield in advanced process technologies (like the 45 nm and beyond technological nodes) [2]. Moreover, the yield loss is also expected to grow in the future technology nodes where physical device parameters will approach the atomic scale and therefore will be subject to atomic uncertainties [1].…”

Section: Introductionmentioning

confidence: 99%

“…This ability, to achieve very high integration density, has contributed to the success of integrated circuit (IC) design during the past few decades. Unfortunately, technology scaling is leading to a significant increase in process variability due to random doping effects, imperfections in lithographic patterning of small devices, and related effects [1]. Process variations (PVs) introduce statistical inter-die/intra-die fluctuations both in physical properties (e.g., transistor threshold voltage and transconductance, interconnect resistances and capacitances) and geometries of the different layers, which in turn result in uncertainties in speed and power characteristics of ICs [2,3].…”

Section: Introductionmentioning

confidence: 99%

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Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations

Lanuzza

Frustaci

Perri

et al. 2011

JLPEA

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Abstract:Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of energy aware adder circuits. Five well known adder circuits were designed exploiting an industrial 45 nm static complementary metal-oxide semiconductor (CMOS) standard cell library. The designed adders were comparatively evaluated under different energy constraints. As a main result, the performed analysis demonstrates that, for a given energy budget, simpler circuits (which are conventionally identified as low-energy slow architectures) operating at higher power supply voltages can achieve a timing yield significantly better than more complex faster adders when used in low-power design with supply voltages lower than nominal.

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Section: Impact Of Intra-die Process Variability For Different Power mentioning

confidence: 69%

Section: Timing Yield Issues and Design Guidelines For Energy-aware Amentioning

confidence: 99%

Section: Impact Of Intra-die Process Variability For Different Power mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%