Nano-indentation studies of xerogel and SiLK low-K dielectric materials

Sikder, A. K.; Irfan, I. M.; Kumar, Ashok; Anthony, J. Mark

doi:10.1007/s11664-001-0169-x

Cited by 25 publications

(10 citation statements)

References 13 publications

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“…(a) Representative strain vs stress plot of a hollow alumina nanolattice. (b and c) Young’s modulus vs dielectric constant plots of the nanolattice compared with other low- k materials. ,,− ,− …”

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confidence: 99%

Enabling Simultaneous Extreme Ultra Low-k in Stiff, Resilient, and Thermally Stable Nano-Architected Materials

et al. 2017

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(GIST), Gwangju 61005, Korea † These authors have contributed equally to this work.Keywords: dielectric constant, low-k, nanolattice, porosity, Young's modulus. AbstractLow dielectric constant (low-k) materials have gained increasing popularity because of their critical role in developing faster, smaller, and higher performance devices. Their practical 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2 use has been limited by the strong coupling between mechanical, thermal, and electrical properties of materials and their dielectric constant; low-k is usually attained by materials that are very porous, which results in high compliance, i.e. silica aerogels, 39 high dielectric loss, i.e.porous polycrystalline alumina, 25 and poor thermal stability, i.e. Sr-based metal-organic frameworks. 23 We report the fabrication of 3D nano-architected hollow-beam alumina dielectrics whose k is 1.06-1.10 at 1MHz that is stable over the voltage range of -20V to 20V and a frequency range of 100 kHz to 10 MHz. This dielectric material can be used in capacitors and is mechanically resilient, with a Young's modulus of 30 MPa, a yield strength of 1.07 MPa, a nearly full shape recoverability to its original size after >50% compressions, and outstanding thermal stability with a thermal coefficient of dielectric constant (TCK) of 2.43 × 10 -5 K -1 up to 800 °C. These results suggest that nano-architected materials may serve as viable candidates for ultra low-k materials that are simultaneously mechanically-resilient, and thermally and electrically stable for microelectronics and devices. Main TextDesigning and synthesizing low dielectric constant (low-k) materials has been a subject of intense research because of their potential use in high performance technological applications like computer processing, 1,2 wireless communications, [3][4][5][6] and automotive radar. 7 Lowering the k of the interlayer dielectric decreases the resistance-capacitance (RC) delay, lowers power consumption, and reduces cross-talk between nearby interconnects, all of which pose significant issues for modern integrated circuits (ICs). [8][9][10] The low-k property is also favored in low temperature co-fired ceramic (LTCC) technology and represents the backbone of Multi Chip Module (MCM) technology, which enables the integration of passive elements like inductors, 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 3 resistors, and capacitors, which serve as building blocks for 3D circuits for the microwave/millimeter communications industry. [11][12] For example, the antenna in a typical RF module for radiating/receiving radio waves, requires the supporting substrate whose k is sufficiently low to preven...

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Enabling Simultaneous Extreme Ultra Low-k in Stiff, Resilient, and Thermally Stable Nano-Architected Materials

et al. 2017

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“…Details of the measurement technique have been discussed elsewhere. 20 The surface and grain-boundary characteristics of the EP copper films were studied using AFM (Dimension 3100, Digital Instruments, Veeco Instruments, NY). The tribological properties of all the EP copper films were also measured using the Bench Top CMP tester.…”

Section: Methodsmentioning

confidence: 99%

Effect of multistep annealing on mechanical and surface properties of electroplated Cu thin films

Sikder

Kumar

Shukla

et al. 2003

Journal of Elec Materi

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“…[20][21][22][23] This is a depthsensing indentation at low loads and is a well-established technique for the investigation of localized mechanical behavior of materials. [20][21][22][23] This is a depthsensing indentation at low loads and is a well-established technique for the investigation of localized mechanical behavior of materials.…”

Section: Methodsmentioning

confidence: 99%

Mechanical and tribological properties of interlayer films for the damascene-Cu chemical-mechanical planarization process

Sikder

Kumar

2002

Journal of Elec Materi

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Chemical-mechanical planarization (CMP) is a key technology for the Cu-damascene wiring process in integrated circuit (IC) manufacturing. 1-3 Chemical-mechanical planarization (CMP) is important for the semiconductor industry in manufacturing six or more levels of multilevel interconnects with critical dimensions of sub-one-tenth micron. In general, each silicon wafer is exposed to 15 or more CMP steps prior to final device assembly. During CMP, the wafer is pressed face down against a rotating polishing pad, while a chemically and physically active slurry planarizes the wafer. As wafer size grows, device sizes shrink, process requirements become more rigorous, and the uniformity within die/wafer and the CMP removal rate become a greater concern. Often, a change in slurry or operating conditions leads to conflicting results. Hence, there is a need for a better understanding of all the complex tribological interactions among slurry, polishing pad, wafer, and pad conditioner. Fundamental tribological studies and characterization of consumables allow the optimization of the pad design, material selection, process pressure, orbital and linear speed, chemical solution, within-wafer uniformity, and local planarization. [4][5][6][7][8] With the shrinkage of the device dimension and the increase in device density, low dielectric-constant (low-k) materials have attracted enormous interest because they can minimize the propagation delay, interconnect capacitance, and cross talk between signal lines for deep submicron ICs. 9-11 Various low-k materials are emerging as potential replacements for SiO 2 . In addition, electrically more conductive Cu has replaced Al metallization to reduce the overall RC (resistance-capacitance) delay. 12,13 Although the device performance will improve by using low (k Ͻ 3) films along with Cu metallization, several problems need to be solved from

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Nano-indentation studies of xerogel and SiLK low-K dielectric materials

Cited by 25 publications

References 13 publications

Enabling Simultaneous Extreme Ultra Low-k in Stiff, Resilient, and Thermally Stable Nano-Architected Materials

Enabling Simultaneous Extreme Ultra Low-k in Stiff, Resilient, and Thermally Stable Nano-Architected Materials

Effect of multistep annealing on mechanical and surface properties of electroplated Cu thin films

Mechanical and tribological properties of interlayer films for the damascene-Cu chemical-mechanical planarization process

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