2021
DOI: 10.1021/acsanm.1c00773
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Nano-Ridge Bending during Conformal Ruthenium Metallization: Implications for Interconnect Fabrication

Abstract: Conformal deposition of ruthenium in a damascene-like approach has shown promising results to form Ru nanowires with superior resistive and reliability characteristics for application as interconnects in very large-scale integrated circuits. Nevertheless, the mechanical integrity of nanostructures during process development for novel materials' integration is paramount. In this paper, a mechanism of dielectric pattern distortion is identified, which occurs during conformal deposition of ruthenium and cannot be… Show more

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Cited by 2 publications
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“…This chapter looks at the material properties of thin Ru films from the perspective of their suitability for use as an inert electrode in ReRAM cells, such as Cu/TaO x /Ru [1], that lends itself to be readily integrated in the CMOS back-end-of-line (BEOL) [2]. Advanced interconnects at 10 nm half-pitch, in order to overcome the scaling issues with Cu interconnects, increasingly pin hopes on ruthenium metallization, not only as a liner and diffusion barrier for Cu, but also as a stand-alone material for contact plug, via, and even interconnect lines [3][4][5]. Such integration of ReRAM memory into BEOL has the potential of reducing the latency in connectivity-constrained computational devices and of bringing logic and memory closer together [6][7][8].…”
Section: Introductionmentioning
confidence: 99%
“…This chapter looks at the material properties of thin Ru films from the perspective of their suitability for use as an inert electrode in ReRAM cells, such as Cu/TaO x /Ru [1], that lends itself to be readily integrated in the CMOS back-end-of-line (BEOL) [2]. Advanced interconnects at 10 nm half-pitch, in order to overcome the scaling issues with Cu interconnects, increasingly pin hopes on ruthenium metallization, not only as a liner and diffusion barrier for Cu, but also as a stand-alone material for contact plug, via, and even interconnect lines [3][4][5]. Such integration of ReRAM memory into BEOL has the potential of reducing the latency in connectivity-constrained computational devices and of bringing logic and memory closer together [6][7][8].…”
Section: Introductionmentioning
confidence: 99%