Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Ayala, Christopher L.; Grogg, Daniel; Bazigos, Antonios; Bleiker, Simon J.; Fernández-Bolaños, Montserrat; Niklaus, Frank; Hagleitner, Christoph

doi:10.1016/j.sse.2015.05.029

Cited by 11 publications

(7 citation statements)

References 28 publications

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“…This configuration can be realized, for example, by a ''via-last'' heterogeneous 3-D integration process as outlined in Fig. 2, in which the silicon device layer of a silicon-on-insulator (SOI) wafer is transferred to a wafer containing a metal interconnect stack (and CMOS circuits where required) from a standard CMOS foundry offering [13], [16]. Consequently, vias 1 and NEM relays are formed.…”

Section: Technology Platform and Modelingmentioning

confidence: 99%

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Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

et al. 2018

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The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 • C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 µm, on-resistance of 200 k , and a via pitch of 0.4 µm, all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.

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Section: Technology Platform and Modelingmentioning

confidence: 99%

“…Such integration of NEM relay circuits can be achieved by approaches that can be collectively [12]. classified as monolithic integration [7]- [11], or heteogeneous integration [12], [13].…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

et al. 2018

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“…Functional digital gates and circuits based on in-plane as well as out-of-plane relays have also been reported [8,9]. While stiction in the contact and overall reliability are major issues, significant progress has been made [10].…”

Section: Introductionmentioning

confidence: 99%

Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits

Qin¹,

Rana²,

Pamunuwa³

2015

2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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University of Bristol -Explore Bristol Research General rightsThis document is made available in accordance with publisher policies. Please cite only the published version using the reference above. ABSTRACTIntegrated circuits based on nano-electromechanical (NEM) relays are a promising alternative to conventional CMOS technology in ultra-low energy applications due to their (near) zero stand-by energy consumption. Here we describe the details of an overarching design framework for NEM relays, including automated synthesis from design entry in RTL to layout, based on commercially available EDA tools and engines. Critical differences between relays and FETs manifest in fundamentally different timing characteristics, which significantly affect static timing analysis and the requisite timing models. The adaptation of existing EDA methods, models, tools and platforms for logic and physical synthesis to account for these differences are described, providing insight into large-scale design of NEM relay-based digital processors. A historically well-known processor, the Intel 4004, and a modern MIPS32 compatible processor are synthesized based on a NEM relay-based standard cell library to demonstrate the customized synthesis methodology. An energy study is carried out using the proposed design framework on benchmark circuits implemented in existing CMOS nodes and NEM node, to better understand the energy saving potential of NEM technology.

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“…A combination of these proposed NEMS switches has been shown to perform the NOR/XOR/NAND and an inverter. Similarly, curved cantilevers are proposed in [20] to realize a single stage inverter and buffer.…”

mentioning

confidence: 99%

Torsion based universal MEMS logic device

Ilyas

Arevalo

Bayes

et al. 2015

Sensors and Actuators A: Physical

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Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts

Cited by 11 publications

References 28 publications

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

Design methodologies, models and tools for very-large-scale integration of NEM relay-based circuits

Torsion based universal MEMS logic device

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