NanoMagnet Logic: An Architectural Level Overview

IEEE Trans. Nanotechnology

et al. 2016

Self Cite

With the predicted end of CMOS scaling process, researchers started to study several alternative technologies. Among them NanoMagnet Logic (NML) offers advantages complementary to MOS transistors especially for its magnetic nature. Its intrinsic memory capability makes it suitable for zero stand-by power and logic-in-memory applications. NML requires a clock system that, if based on a magnetic field, highly increases the circuit dynamic power consumption. We have recently proposed a solution based on the magnetoelastic effect (ME-NML) [1] and on currently available fabrication processes, which drastically reduces dynamic power consumption. However, many questions still remain unanswered. Which kind of applications are best suited for this technology? How can we effectively design, analyze and compare ME-NML circuits? Does it really offer advantages over state-of-the-art CMOS transistors? In this paper we provide answers to all these questions and the results prove that this technology offers indeed extremely good performance. We have designed a Galois Field Multiplier with a systolic array structure to reduce interconnection overhead. We developed a new RTL model that allows us to easily describe and simulate circuits of any complexity, evaluating at the same time the performance and keeping into account technology constraints. We approach for the first time in the NML scenario the design of ME-NML circuits adopting the standardcell method used in standard technologies and fulfill the design down to the physical level. The same circuit is designed also with NML technology based on magnetic fields and with a 28 nm low power CMOS bulk technology for comparison. The CMOS circuit is obtained through physical place&route with a commercial tool, providing therefore the most accurate comparison ever presented in literature. Power analysis shows that ME-NML circuits have a considerable advantage over both NML and state of the art CMOS bulk technology. As a further by-product results clearly highlight which kind of architectures can better exploit the true potential of NML technology.

Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Modeling, Design, and Analysis of MagnetoElastic NML Circuits

Giri

IEEE Trans. Nanotechnology

et al. 2016

Self Cite

“…As a consequence a multiplication can be completed in 6N clock cycles, where N is the multiplier number of bits. To improve data throughput, signals interleaving can be adopted [3]. Six multiplications must be executed in parallel, so at every clock cycle a new data from a different multiplication must be fed to the circuit.…”

Section: A Magnetoelastic Gfmmentioning

confidence: 99%

“…1.A) and they can be used to represent logic values [2]. Since the basic cell is a magnet, NML couples logic and memory in the same device [3]. Moreover it is one of the few emerging technologies that is feasible with current technological processes [2] and works at room temperature.…”

Section: Introductionmentioning

confidence: 99%

A standard cell approach for MagnetoElastic NML circuits

Giri

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

et al. 2014

Among emerging technologies Quantum dot Cellular Automata (QCA) plays a fundamental role. Its magnetic version, normally called NanoMagnet Logic (NML), is particularly interesting thanks to the ability to work at room temperature and to mix logic and memory in the same device. Magnetic circuits have also a potential very low power consumption. Unfortunately classic NML circuits are normally driven (clocked) with a current generating a clocked magnetic field, nullifying the possibility to actually obtain low power circuits.We have recently developed a technology-friendly solution, the MagnetoElastic NML (ME-NML), where magnetic circuits are driven through an electric field, and not with a current, drastically reducing the power consumption. In this paper we start to explore the architectural consequences of this new magnetic technology. The analysis is performed using as a benchmark a Galois multiplier, a systolic architecture particularly suited for QCA and NML technologies. The layout is precisely described and the resulting circuit is modeled and simulated using VHDL language. The obtained results are remarkable. The circuit area is reduced by 4 times compared to classic NML approach. This, coupled with the intrinsic lower power consumption due to different clock, leads to a 50 times reduction of power absorption. Moreover the particular structure of magnetoelastic NML allows to define a library of standard cells that can be easily used by designers and automatic layout tools to design circuits, greatly improving future research in this field.

“…2.C. The main logic functions are implemented using AND, OR and inverters [13], while a crosswire block [8] is required to cross two wires on the same plane, since NML is a single layer technology. We have envisioned the LIM architecture as a multi-dimensional structure, where logic, memory and interconnections are placed on different planes.…”

Section: Nanomagnet Logicmentioning

confidence: 99%

Logic-in-Memory architecture made real

Pala

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

et al. 2015

The current trend for intensive computational architectures is to adopt massive parallelism, with several concurrent tasks performed simultaneously, as done for example in GPUs. This approach has many advantages, such as the reduced design time given by circuit replication and an increasing in computational speed without the need of higher frequency. It has however evidenced an important bottleneck in data exchange between memory and processor.We envisage a revolutionary path for the future relation between memory and logic in parallel processors, where a new type of architecture exploits the principle of caching to the limit. Our Logic-in-Memory (LIM) architecture mixes logic and memory in the same device, removing the bottleneck of other existing parallel solutions. The architecture we propose, here in its preliminary version, has an array organization and each element in the array is based on three blocks: a logic unit for processing, a smart memory block and a routing structure for inter block communication. In this article we show the benefits of this approach with an application example in the image processing field. We can achieve a 4X computational time reduction for an image processing algorithm (Summed Area Table) with respect to the best architecture present in the literature, even with a preliminary and not optimized version.Besides the adoption of massive parallelism to increase performance, new technologies to open the post-CMOS era are explored. Among them NanoMagnet Logic (NML) is particularly interesting for its ability to mix logic and memory in the same device. We present here the preliminary results of the NML implementation of the LIM architecture. We thus demonstrate that it is not only a good solution for a standard CMOS technology but can also exploit the potential of an emerging technology as NML.