Nanoribbon‐Based Flexible High‐Performance Transistors Fabricated at Room Temperature

Abstract

if their application is limited to small and compact areas as for economic reasons and integration related difficulties it is not practical to have them over the large areas. As a result, the printed devices and circuits based on nanostructures (NSs) of highmobility materials such as Si nanowires (NWs), Si nanoribbons (NRs), carbon nanotubes (CNTs), GaAs NWs, etc. have been explored. [12][13][14] The excellent performance (e.g., high mobility and On/Off ratio) offered by some of the NS-based devices is summarized in Table 1. A major challenge with NSs based devices is that some of the critical fabrication steps (e.g., NSs fabrication/growth, doping, high-k dielectric deposition) require high-temperatures that are incompatible with the flexible substrates such as plastics.Currently, the popular method to address this issue is to transfer print NSs from the native or growth substrates to the receiving flexible substrate using a stamp or career substrate. [12,15,16] Since the high temperature fabrication steps are carried out before transfer (i.e., when NSs are still on the native or growth substrates), this method decouples the high temperature process steps from the low-temperature steps (e.g., metallization) that are carried out after transfer to realize devices on flexible substrates, as shown in Figure 1. Previous works have carried out most of the steps, including high temperature dielectric deposition which yielded good device characteristics, [17,18] before transfer printing. Transfer printing of such fully formed field effect transistors (FETs) increases the process complexities which also raises the technology cost. An alternative method is to use substrates such as metal foils, which can withstand higher processing temperatures. However, additional fabrication steps such as insulation on foils increase the cost of fabrication and for this reason manufacturing through low-temperature processing steps is preferred. The low-temperature processing keeps the transfer printing process highly robust and could aid fabrication of FETs over large area flexible substrates as it is compatible with methods such as roll-to-roll technology. Thus, key challenge is to develop high-performance NRFET by dielectric deposition preferably at room temperature (RT). Many experimental techniques, such as atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced (PE)-CVD, inductively coupled plasma (ICP)-CVD, e-beam evaporation, etc., have been successfully used to develop high quality dielectric films in the past. [19] ALD and LPCVD techniques typically use growth temperatures in Si-nanoribbon-based high-performance field-effect transistors (FETs) with room temperature (RT)-deposited dielectric are presented. The distinct feature of these devices is that the high-quality SiN x dielectric deposition at RT, directly on the transfer-printed nanoribbons, is compatible with most flexible substrates. The performance of these FETs (mobility ≈656 cm 2 V −1 s −1 and on/off ratio >10 6 ) is on par with ...

High-performance printed electronics based on inorganic semiconducting nano to chip scale structures

“…Top-down methods have also been used to obtain horizontally aligned NRs/NMs from SOI wafer with thickness ranging from few 'nms' to few tens of nm and lateral dimensions between few tens of µm to mm. Their fabrication process involves anisotropic wet or dry etching of selected exposed regions on the top side of Si wafer, and then undercut removal of the buried oxide (BOX) with hydrofluoric acid to release Si NRs or NMs structures [46,[97][98][99][100]. Figure 4b illustrates one such example where the optical lithography and wet chemical etching steps are followed to obtain Si NRs from commercial SOI wafer [46].…”

“…Their fabrication process involves anisotropic wet or dry etching of selected exposed regions on the top side of Si wafer, and then undercut removal of the buried oxide (BOX) with hydrofluoric acid to release Si NRs or NMs structures [46,[97][98][99][100]. Figure 4b illustrates one such example where the optical lithography and wet chemical etching steps are followed to obtain Si NRs from commercial SOI wafer [46]. This technique produces horizontal array of NRs over SOI source wafers and these are eventually transfer printed over flexible substrates.…”

“…A wet etching method using hydrofluoric acid is performed to remove both dopant diffusion barrier layer and buried oxide layer leading in release of the NRs from the bulk wafer, allowing the selectively doped NRs to be transfer printed to any flexible substrate. Adapted with permission from [46]. c Schematic illustration of the fabrication of NWs/NMs by use of anisotropic wet-chemical etching techniques applied to bulk wafers which is not available for many technologically important III-V and oxide semiconductors.…”

“…microwires (MWs)) and chip (e.g. ultra-thin chips (UTCs)) scale structures [25,26,[42][43][44][45][46][47][48][49][50][51][52][53]. These nano/micro/chip scale structures are typically single-crystalline and result in high-performance electronics.…”

“…These nano/micro/chip scale structures are typically single-crystalline and result in high-performance electronics. For instance, the mobility (in cm 2 /V•s) of about 270 for n-type Si-NWs [54], 300 for p-type Si NWs, 730 for Ge/Si core/shell NWs [55] and 660 for Si NRs [46] have been demonstrated. The transfer printing (TP) and contact printing (CP) methods developed to transfer or print these structures onto flexible substrates could address the traditional thermal budget issue associated with the inorganic semiconducting materials i.e.…”