Nanoscale modules with full spin-wave interconnectivity

Eshaghian‐Wilner, Mary Mehrnoosh; Khitun, A.; Navab, Shiva; Wang, K. L.

doi:10.1080/17458080601013504

“…In turn, the change of magnetic field as a function of time results in an inductive voltage [8]. There is a lot of work done to physically and experimentally show the generation/excitation [13], [14], propagation [15], [16] and detection [17] of spin waves, nevertheless none of these publications focuses on the scaling challenges of the devices. Also there is a considerable body of work on the circuit design aspects of spin wave devices [3], [18].…”

Section: A Spin Wave Basicsmentioning

confidence: 99%

System-level assessment and area evaluation of Spin Wave logic circuits

Zografos¹,

Raghavan²,

Amarù³

et al. 2014

2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)

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Spin Wave Devices (SWDs) are promising candidates for scaling electronics beyond the domain of CMOS. In contrast to traditional charge-based technologies, SWDs rely on propagating oscillation of magnetization as information carrier. Thanks to the intrinsic wave computation capability of these devices, the majority gate is implemented with low physical resources. Being more expressive than standard NAND/NOR gates, the compact majority gate pushes further the expected benefits of SWDs over CMOS. In this paper, we present a realistic design framework for SWD-based logic circuits, accounting for both limitations and advantages deriving from the new technology. We use a majority logic synthesis tool to fully exploit the SWD functionality. In the experiments, we focus on the estimated area. We consider several arithmetic-intensive benchmarks, and compare their SWD area with three state-of-the-art CMOS nodes. We show that an area reduction up to 11.3× is possible, as compared to a 10nm CMOS technology.

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“…To copy otherwise, to republish, to post on servers, or to redistribute to lists, requires prior specific permission and/or a fee. the generation/excitation [13], [14], propagation [15], [16] and detection [17] of spin waves, nevertheless none of these publications focuses on the scaling challenges of the devices. Also there is a considerable body of work on the circuit design aspects of spin wave devices [3], [18].…”

Section: A Spin Wave Basicsmentioning

confidence: 99%

System-level assessment and area evaluation of spin wave logic circuits

Zografos

¹

,

Raghavan

²

,

Amarù

³

et al. 2014

Proceedings of the 2014 IEEE/ACM International Symposium on Nanoscale Architectures

View full text Add to dashboard Cite

Spin Wave Devices (SWDs) are promising candidates for scaling electronics beyond the domain of CMOS. In contrast to traditional charge-based technologies, SWDs rely on propagating oscillation of magnetization as information carrier. Thanks to the intrinsic wave computation capability of these devices, the majority gate is implemented with low physical resources. Being more expressive than standard NAND/NOR gates, the compact majority gate pushes further the expected benefits of SWDs over CMOS. In this paper, we present a realistic design framework for SWD-based logic circuits, accounting for both limitations and advantages deriving from the new technology. We use a majority logic synthesis tool to fully exploit the SWD functionality. In the experiments, we focus on the estimated area. We consider several arithmetic-intensive benchmarks, and compare their SWD area with three state-of-the-art CMOS nodes. We show that an area reduction up to 11.3× is possible, as compared to a 10nm CMOS technology. NANOARCH '14,

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“…In this section, a nanoscale crossbar architecture that is interconnected with ferromagnetic spin-wave buses is introduced [7,8]. The power consumption of these proposed modules is relatively low, and the classical type of computing, as opposed to quantum, is employed.…”

Section: Spin-wave Crossbarmentioning

confidence: 99%