Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

Abstract

Abstract-This paper presents the simplified charge-based EKV MOSFET model and shows that it can be used for advanced CMOS processes despite its very few parameters. The concept of inversion coefficient IC is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT 0 and spans the entire range of operating points from weak via moderate to strong inversion, including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40-nm and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation valid from weak to strong inversion and requiring only the VS parameter λc is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuit, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to strong inversion with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance G ds /ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for DIBL. The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted SOI (FDSOI) and FinFET 28-nm processes.

Characterization and Modeling of Gigarad-TID-Induced Drain Leakage Current of 28-nm Bulk MOSFETs

“…The simplified EKV MOSFET model is able to fully describe large-and small-signal characteristics over a wide range of bias from weak via moderate to strong inversion with only four parameters-i.e., the slope factor n, the specific current I spec , the velocity saturation parameter λ c , and the threshold voltage V T0 . References [11], [30], [31] have verified the applicability of this model for this commercial 28-nm bulk CMOS process. Since the gateless charge-controlled concept involves no gate voltage or gate oxide capacitance, we need to modify the simplified EKV MOSFET model for the lateral parasitic n-QFET.…”

A design-oriented charge-based simplified model for FDSOI MOSFETs

“…As a starting point, the simplified EKV model is considered [2]. In order to recall it, its derivation basics are cited below.…”

“…Due to this fact, conventional design methodologies have been revised in order to exploit at best all the features of advanced technologies [1]. In that sense, the simplified EKV model (sEKV) [2], [3], based on the inversion coefficient (IC), has demonstrated its effectiveness in describing the performance of MOSFETs in all inversion conditions while using only a few parameters. The key of this capability, together with the charge-related basis, is the normalization, that strips off the dependence to a specific technology which is then captured by only a few parameters.…”

“…The key of this capability, together with the charge-related basis, is the normalization, that strips off the dependence to a specific technology which is then captured by only a few parameters. This makes the simplified EKV model suitable also as a benchmark for technologies, in addition to helping the designer to explore the design space and find the right trade-off in terms of design parameters [2].…”

“…finFET and FDSOI processes [4], [5]. If in the case of finFET, the sEKV bulk model is still suitable [2], for FDSOI back-gate effects have to be considered. Therefore, this further degree of freedom has been addressed through a re-adaptation of the sEKV model, so that the design flow can directly focus on the performance trade-offs linked also to the back-gate biasing.…”