Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling

Veloso, A.; Eneman, G.; Keersgieter, A. De; Jang, Doyoung; Mertens, Hans; Matagne, Philippe; Litta, Eugenio Dentoni; Ryckaert, Julien; Horiguchi, N.

doi:10.1109/edtm50988.2021.9420942

Cited by 15 publications

(5 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Furthermore, short-channel effects are less significant in three-dimensional structures such as fin, multi-gate, gate-all-around, and nanosheet field-effect transistors, where the gate control is substantially improved. It was recently suggested that forksheet field-effect transistors and stacked complementary metal-oxide semiconductors with the three-dimensional sequential technology can significantly reduce p–n separation and improve cell area scaling. , …”

Section: Introductionmentioning

confidence: 99%

“…It was recently suggested that forksheet field-effect transistors and stacked complementary metal-oxide semiconductors with the three-dimensional sequential technology can significantly reduce p−n separation and improve cell area scaling. 4,7 Two-dimensional semiconductor transition-metal dichalcogenide materials (e.g., MoS 2 ) offer bottom-up solutions to some of the technical and fundamental problems faced by the top-down Si-based industry. Specifically, transition-metal dichalcogenides exhibit good surface roughness without dangling bonds, along with a desirable bandgap (1−2 eV) for electronic and optical applications.…”

Section: ■ Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Jeon

Park

et al. 2023

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

Junctionless transistors are suitable for sub-3 nm applications because of their extremely simple structure and high electrical performance, which compensate for short-channel effects. Two-dimensional semiconductor transition-metal dichalcogenide materials, such as MoS2, may also resolve technical and fundamental issues for Si-based technology. Here, we present the first junctionless electric-double-layer field-effect transistor with an electrostatically highly doped 5 nm thick MoS2 channel. A double-gated MoS2 transistor with an ionic-liquid top gate and a conventional bottom gate demonstrated good transfer characteristics with a 104 on–off current ratio, a 70 mV dec–1 subthreshold swing at a 0 V bottom-gate bias, and drain-current versus top-gate-voltage characteristics were shifted left significantly with increasing bottom-gate bias due to an electrostatically increased overall charge carrier concentration in the MoS2 channel. When a bottom-gate bias of 80 V was applied, a shoulder and two clear peak features were identified in the transconductance and its derivative, respectively; this outcome is typical of Si-based junctionless transistors. Furthermore, the decrease in electron mobility induced by a transverse electric field was reduced with increasing bottom-gate bias. Numerical simulations and analytical models were used to support these findings, which clarify the operation of junctionless MoS2 transistors with an electrostatically highly doped channel.

show abstract

Section: Introductionmentioning

confidence: 99%

Section: ■ Introductionmentioning

confidence: 99%

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Jeon

Park

et al. 2023

ACS Appl. Mater. Interfaces

View full text Add to dashboard Cite

show abstract

“…In the semiconductor industry, researchers have been exploring new engineering architectures to address the challenges of scaling. These include innovations such as double gate, gate all around, quadruple gate, dual material double gate, triple material double gate, and nano-sheet FET [4], among others. Simultaneously, efforts have been made to improve electrostatic control and mitigate issues like short-channel effects (SCE), parasitic capacitance, and 𝐼 ON /𝐼 OFF ratio.…”

Section: Introductionmentioning

confidence: 99%

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

Abbasnezhad,

Saghai,

Hosseini

et al. 2023

Journal of Electrical Engineering

View full text Add to dashboard Cite

In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (C gg), transconductance g m, and cut-off frequency (f T) for all three device types. In our Proposed GAA NS FET, we employ Germanium for the source and substrate regions, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon for the drain region. The introduction of strain into the nanosheet and the use of a heterojunction structure significantly enhance device performance. Before utilizing a model to analyze a semiconductor device, it is crucial to accurately determine and elaborate on the model parameters. In this case, we solve the Density Gradient (DG) equation self-consistently to obtain the electrostatic potential for a given electron Fermi-level distribution, use the Shockley-Read-Hall (SRH) equation to estimate carrier generation, account for bandgap narrowing in transport behavior, and consider auger recombination. Our general results indicate a notable improvement in drain current, transconductance, and unity-gain frequency by approximately 42%, 53%, and 31%, respectively. This enhancement results in superior RF performance for the Proposed GAA NS FET compared to both the heterojunction GAA NS FET and the conventional GAA NS FET.

show abstract

“…Future CMOS technology nodes will rely on Gate-All-Around (GAA) FETs that ensure ultimate control over the short-channel effects (1)- (3). In this class of devices, GAA Vertical Nanowires (VNWs) offer some clear integration advantages over horizontal architectures.…”

Section: Introductionmentioning

confidence: 99%

“…In this class of devices, GAA Vertical Nanowires (VNWs) offer some clear integration advantages over horizontal architectures. While their integration requires a somewhat more complex processing scheme (4), these devices can be implemented in a 3D architecture, for example, as selectors in memory circuits (3). When fabricating VNW transistors on a bulk substrate, the latter serves at the same time as the source, using a backside contact.…”

Section: Introductionmentioning

confidence: 99%

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

Simoen¹,

Veloso²,

Matagne³

et al. 2021

ECS Trans.

View full text Add to dashboard Cite

This paper gives an overview of the impact of certain processing steps on the low-frequency (LF) noise behavior of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) MOS transistors. It is shown that the width of a Replacement Metal Gate (RMG) cap impacts the flicker noise Power Spectral Density (PSD). The type of source contact, i.e., bulk versus a confined top contact significantly changes the nature and the magnitude of the 1/f noise. Finally, the doping density of the silicon nanowires has a subtle influence, whereby the dominant fluctuation mechanism shifts from number to mobility fluctuations, while increasing the doping density. Optimal noise performance is achieved for intermediate in-situ nanowire B doping density.

show abstract

Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling

Cited by 15 publications

References 3 publications

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

Contact Info

Product

Resources

About

Nanosheet FETs and their Potential for Enabling Continued Moore's Law Scaling

Cited by 15 publications

References 3 publications

Junctionless Electric-Double-Layer MoS2 Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Junctionless Electric-Double-Layer MoS2 Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

Contact Info

Product

Resources

About

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel

Junctionless Electric-Double-Layer MoS₂ Field-Effect Transistor with a Sub-5 nm Thick Electrostatically Highly Doped Channel