Nanowire & nanosheet FETs for ultra-scaled, high-density logic and memory applications

First Demonstration of Novel Vertical Gate-All-Around Field-Effect-Transistors Featured by Self-Aligned and Replaced High-κ Metal Gates

“…Lateral and vertical nanowires/nanosheets (NWs/NSs) are the typical structures of GAAFETs, which have excellent electrostatic properties and short channel control. − Compared with lateral devices, vertical GAAFETs (vGAAFETs) have free flexibility design on gate length, reduced area, and parasitic capacitance; , thus, they have great potential for 3D integration and PPAC scaling . Moreover, they have advantages over FinFETs as the selector transistors in nonvolatile memory technology such as MRAM for the 3 nm node . However, the fabrication of vGAAFETs is still challenging, such as metal contamination, accurate gate-length control, the alignment of the gate with the channel, and doping strategies in channel and source/drain regions (S/D). ,− To solve the problem of metal contamination, top-down technology was introduced. , Toward the gate-related technology, in some gate-first processes, the integration of high-κ dielectrics and metal gates is difficult .…”

Ge0.95Sn0.05 Gate-All-Around p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors with Sub-3 nm Nanowire Width

“…Over the past few decades, the advancement of integrated chip industry has been driven by aggressive dimension downscaling of complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) as predicted by Moore’s Law. , Other key innovations, including strained Si, high- k /metal gate, and FinFET architecture were also introduced after the gate length entered sub-100 nm regime. − Three-dimensional (3D) FinFET was first introduced at 22 nm technology node in 2011 and is still employed at today’s most cutting-edge 5 nm CMOS platform by TSMC . 3D MOSFETs with multigate structures have advantages of good control of short channel effects (SCEs) as well as superior scalability using conventional large-scale manufacturing processes. ,− The gate-all-around (GAA) architecture (nanowire or nanosheet) is strongly desired to enable further scaling to the 3 nm technology node and beyond, as it offers the ultimate capability for gate electrostatic control over the channel, and thus superior immunity to SCEs. − …”

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

“…Table I. These values are chosen under the feasible condition for vertical NWFETs [10], [11]. Before parameter randomization, n-and p-type NWFETs are calibrated to Samsung NWFETs [18] as shown in Fig.…”

“…Meanwhile, vertical NWFET is one of the promising candidates which can have device design flexibility by large CPP margin since the channel is aligned vertically [8]- [11]. In addition, vertical NWFETs along with BPR possibly ease 3D MOL layout schemes by forming power delivery lines at the bottom.…”

“…In addition, vertical NWFETs along with BPR possibly ease 3D MOL layout schemes by forming power delivery lines at the bottom. Vertical NWFETs have great potential to increase the device density by aligning transistors and selectors vertically [11]- [14]. However, since the fabrication flows are different from conventional horizontal FETs, it is needed to optimize the device structure to boost its performance and finally to provide the device guideline.…”