Nanowire gate-all-around MOSFETs modeling: ballistic transport incorporating the source-to-drain tunneling

Abstract

Incorporating the source-to-drain tunneling current that is valid in all operating regions, an analytical compact model is proposed in this paper for cylindrical ballistic gate-all-around n-type metal-oxide-semiconductor field-effect transistors with ultra-short silicon channel. From taking the drain-induced barrier lowering effect into consideration, the potential distribution within the device channel has been modeled based upon a 2D analysis in our previous work. In this study, by introducing a parabolic function when modeling the potential profile in the channel direction, we found out that the source-to-drain tunneling effect in the subthreshold region could be evaluated analytically by applying Wentzel–Kramers–Brillouin approximation. Then, it is practical to estimate the ballistic drain current for all operating regions analytically with this compact model considering both the source-to-drain tunneling and thermionic transport. The resulting analytic compact model is tested against non-equilibrium Green's function simulation using SILVACO, and good accuracy is demonstrated. Finally, we perform an NMOS inverter circuit simulation using HSPICE, when introducing our model to it as a Verilog-A script.

Deep Learning Algorithms for the Work Function Fluctuation of Random Nanosized Metal Grains on Gate-All-Around Silicon Nanowire MOSFETs

“…[2]. To keep up the continuous downscaling of Si transistors for high-performance applications, gate-all-around (GAA) Si nanowire (NW) metal-oxide-semiconductor field-effect transistor (MOSFETs) are considered as an arising aspirant among the nanodevices due to predominant electrical characteristics [6]. The fluctuation of electrical characteristic plays a significant role in the field of nanoelectronics.…”

Unified Model of Shot Noise in the Tunneling Current in Sub-10 nm MOSFETs

“…Advances in nanofabrication technology have opened up the possibility of surpassing the ultimate performance limits of modern CMOS devices [1,2]. However, the sub-10 nm channel length in MOSFETs gives rise to tunneling current and associated shot noise through the source-to-drain (SD) potential barrier [3][4][5][6][7][8][9][10][11][12][13][14][15]. With the downscaling of device dimensions, the continuous reduction in gate oxide thickness leads to enormous gate tunneling currents and noise [16][17][18][19][20][21][22][23].…”

“…With the downscaling of device dimensions, the continuous reduction in gate oxide thickness leads to enormous gate tunneling currents and noise [16][17][18][19][20][21][22][23]. Therefore, the off-state currents, from which the static power dissipated by MOSFETs originates, are enhanced by the direct tunneling current through the SD potential and gate oxide in the subthreshold region and consequently prevent low voltage/power operation [5][6][7]. In addition, the miniaturization of nanoscale CMOS logic devices has made the quantum nature of current flow more pronounced, leading to higher fault rates due to shot noise in the subthreshold region [14].…”

Physics-Informed Neural Network for High Frequency Noise Performance in Quasi-Ballistic MOSFETs

“…The HF noise sources in MOSFETs include the thermal drain current noise, due to the channel resistance, giving rise to the induced gate noise and the correlation noise [2][3][4][5][6][7]. In the quasi-ballistic regime, with the channel length comparable to the mean free path length of carriers, there is a tunneling current and its shot noise through the source-todrain (SD) potential barrier [8][9][10][11][12][13][14][15][16][17][18]. Moreover, the continuous reduction of gate oxide thickness leads to tremendous gate tunneling currents and noise [2,[19][20][21][22][23][24].…”

“…These noise sources must be included to accurately predict the overall noise performance for future CMOS technologies, because significant tunneling current and shot noise are expected at normal operating conditions. However, whenever there is a change in the device structure, a complete physical analysis model is required [9,10,13,22], and the parameter extraction of an HF noise model requires a complicated and difficult process [2][3][4]23]. The accuracy and simplicity of an HF noise model is very important for designing RF circuits.…”