Nanowire Volatile RAM as an Alternative to SRAM

Abstract

Maintaining benefits of CMOS technology scaling is becoming challenging due to increased manufacturing complexities and unwanted passive power dissipations. This is particularly challenging in SRAM, where manufacturing precision and leakage power control are critical issues. To alleviate some of these challenges a novel non-volatile memory alternative to SRAM was proposed called nanowire volatile RAM (NWRAM) [1]. Due to NWRAMs regular grid based layout and innovative circuit style, manufacturing complexity is reduced and at the same time considerable benefits are attained in terms of performance and leakage power reduction. In this paper, we elaborate more on NWRAM circuit aspects and manufacturability, and quantify benefits at 16nm technology node through simulation against state-of-the-art 6T-SRAM and gridded 8T-SRAM designs. Our results show the 10T-NWRAM to be 2x faster and 35x better in terms of leakage when compared to high performance gridded 8T-SRAM design.

Experimental prototyping of beyond-CMOS nanowire computing fabrics

“…Fig. 1D and 1E show fabric and circuit schematics of a 10 Transistor Quasi-Static Nanowire RAM (10T -NWRAM) [4] [3]. This circuit implements cross-coupled volatile memory without the need for complementary devices or careful sizing of FETs required in SRAM.…”

“…Benchmarking results of N 3 ASIC logic (a processor design, WISP-0 [1]) showed 3x density and 5x active power benefits against equivalent CMOS design at 16nm [1], and the 10T-NWRAM showed 2x performance and 35x leakage improvement with comparable area and active power, when compared with 16nm CMOS SRAM [3] [4]. These benefits are attained at a significantly relaxed overlay.…”

“…Benchmarking results at 16nm for a processor design show N 3 ASICs to be up to 3x denser and 5x more power efficient than an equivalent CMOS design [1]. Benchmarking results for N 3 ASIC volatile memory shows 2x performance and 35x leakage power benefits, when compared to CMOS SRAM at 16nm [3] [4]. In addition, due to N 3 ASICs regular physical layout and choices at all levels of abstraction, the overlay alignment requirements are significantly less than in CMOS.…”