Narrow Device Issues in Deep-Submicron Technologies-the Influence of Stress, TED and Segregation on Device Performance

Abstract

Shallow Trench Isolation (STI) has been the isolation scheme of choice for sub-0.25µm technologies.One of the challenges of scaling STI to 0.13µm and beyond is the control of Vt and Idsat of narrow devices. In this paper, we show that Idsat of narrow devices is strongly impacted by the stress due to trench processing. We also show that Vt and leakage of narrow devices (in particular NMOS devices) is impacted by dopant redistribution in the channel caused by TED (Transient Enhanced Diffusion) and boron segregation to the trench sidewalls. Device FabricationNarrow devices developed for a 0.15µm technology were used for this study. In this process, a 2900A trench with an 80° slope is etched using an oxide-nitride-SiON hard mask. Bottom trench corners are rounded during the etch. A pad oxide undercut is used to promote the trench corner rounding followed by an RTO liner oxidation at 1150°C. The high temperature liner oxidation is used to minimize stress, achieve a greater than 50nm radius of curvature in the trench corners (Fig 1) and minimize silicon consumption (∆W<0.02µm) [1]. The trench is then filled by an HDP oxide followed by a high temperature N2 densification. An endpoint algorithm and high selectivity slurry are used to improve the CMP uniformity. The transistors use dual doped poly and a 30A nitrided oxide. Nitride spacers and cobalt salicide are used in this process.Transistors were oriented along the [110] direction, normal to the wafer flat. Fig 1-An RTO liner oxide is used to round the trench corners.

Controlling STI-related Parasitic Conduction in 90 nm CMOS and Below

“…The rest of the processing consists in 0.18, 0.13 and 0.09 µm nMOS flows with respective gate oxide thickness (tox) of 3.5, 2.0 and 1.5 nm, related thermal budgets and identical as-implanted channel profile-. Results will be shown on long channel (L=10 µm) nMOS transistors, since they are most sensitive to narrowchannel effects [6].…”

An analytical model for sidewall parasitic capacitance of nano-scale trench isolated MOSFETs

“…2) Dopant redistribution: Dopant redistribution involves two physical phenomena. (i) dopant segregation [15][16] and (ii) transient enhanced diffusion (TED) [17]. Boron segregation reduces the B-concentration near the STI edges.…”