Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

Gu, Jie; Zhang, Qingzhu; Wu, Zhenhua; Luo, Yanna; Cao, Lei; Cai, Yuanlong; Yao, Jiaxin; Zhang, Zhaohao; Xu, Gaobo; Luo, Jun; Wang, Wenwu

doi:10.1109/jeds.2021.3130123

Cited by 16 publications

(4 citation statements)

References 18 publications

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“…Gu et al. [ 38 ] proposed a new etching technique that narrowed the sub-fin with little increase in the processing cost that suppressed the PCE. Their proposed sub-fin design demonstrated a 70% reduction in the sub-channel gate-induced drain leakage and a 20% increase in the on-off current ratio ( I ON / I OFF ), along with an improvement in the SS .…”

Section: Transition From Finfet To Gaafetmentioning

confidence: 99%

New structure transistors for advanced technology node CMOS ICs

Zhang,

Luo

et al. 2024

National Science Review

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Over recent decades, advancements in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) have mainly relied on structural innovations in transistors. From planar transistors to the fin field-effect transistor (FinFET) and gate-all-around FET (GAAFET), more gate electrodes have been added to 3D channels with enhanced control and carrier conductance to provide higher electrostatic integrity and higher operating currents within the same device footprint. Beyond the 1-nm node, Moore’s law scaling is no longer expected to be applicable to geometrical shrinkage. Vertical transistor stacking, e.g. in complementary FETs (CFETs), 3D stack (3DS)-FETs and vertical-channel transistors, for enhanced density and variable circuit or system design represents a revolutionary scaling approach for sustained IC development. Herein, innovative works on specific structures, key process breakthroughs, shrinking cell sizes, and design methodologies for transistor structure research and development are reviewed. Perspectives on future innovations in advanced transistors with new channel materials and operating theories are also discussed.

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Section: Transition From Finfet To Gaafetmentioning

confidence: 99%

New structure transistors for advanced technology node CMOS ICs

Zhang,

Luo

et al. 2024

National Science Review

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“…In recent decades, multi-gate devices have been considered the most promising devices for advanced nodes at 22 nm and beyond, with significant improvements in short-channel effects (SCEs) [1]. Compared to traditional planar MOSFETs, FinFETs exhibit higher driving capability and superior gate control ability, leading to their successful development for highvolume integrated circuits from the 22 nm to 5 nm nodes [2,3]. However, as device sizes scale down to 3 nm and beyond, FinFET faces severe SCEs due to the reduced flexibility of the fins, resulting in challenges to conventional scaling rules.…”

Section: Introductionmentioning

confidence: 99%

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers

Li,

Shao,

Kuang

et al. 2024

Micromachines

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In this work, we propose a SiC-NSFET structure that uses a PTS scheme only under the gate, with SiC layers under the source and drain, to improve the leakage current and thermal reliability. Punch-through stopper (PTS) doping is widely used to suppress the leakage current, but aggressively high PTS doping will cause additional band-to-band (BTBT) current. Therefore, the bottom oxide isolation nanosheet field-effect transistor (BOX-NSFET) can further reduce the leakage current and become an alternative to conventional structures with PTS. However, thermal reliability issues, like bias temperature instability (BTI), hot carrier injection (HCI), and time-dependent dielectric breakdown (TDDB), induced by the self-heating effect (SHE) of BOX-NSFET, become more profound due to the lower thermal conductivity of SiO2 than silicon. Moreover, the bottom oxide will reduce the stress along the channel due to the challenges associated with growing high-quality SiGe material on SiO2. Therefore, this method faces difficulties in enhancing the mobility of p-type devices. The comprehensive TCAD simulation results show that SiC-NSFET significantly suppresses the substrate leakage current compared to the conventional structure with PTS. In addition, compared to the BOX-NSFET, the stress reduction caused by the bottom oxide is avoided, and the SHE is mitigated. This work provides significant design guidelines for leakage and thermal reliability optimization of next-generation advanced nodes.

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“…They became susceptible to SCEs and reliability issues, compounded by fabrication challenges associated with further scaling. GAA NS MOSFETs have since emerged as compelling candidates for sub-5-nm nodes [17,20], offering both superior performance standards and desired capabilities [21,22].…”

Section: Introductionmentioning

confidence: 99%

“…Unlike the upper channels of stacked GAA NS MOSFETs, which are wrapped surrounded gates, the bottom parasitic channel is solely controlled by only the top gate (Fin shape) [30]. Consequently, this channel can function as a leakage path during the off-sate, impacting the overall performance of the GAA NS MOSFETs and circuit [22,31]. To address this concern, recent efforts have focused on various approaches related to suppressing the parasitic leakage in GAA devices, with a particular emphasis on the bottom dielectric isolation (BDI) [27], punchthrough stopper (PTS), buried oxide beneath the gate area [32].…”

Section: Introductionmentioning

confidence: 99%

Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits

Kola,

2023

Preprint

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In this paper, we study the effect of parasitic channel on electrical characteristics and power consumptions of vertically stacked gate-all-around (GAA) silicon nanosheet (NS) MOSFETs of the bulk and silicon-on-insulator (SOI) substrates. Through deliberate control of the bottom parasitic channel coverage, we systematically assess its influence on DC, AC, and RF characteristics including power consumption. The observed findings highlight a significant differentiation among the bottom parasitic channels: GAA (i.e., control sample with 100% coverage), omega-shaped gate NS (70% and 80% coverages), and FinFET (60% coverage). Compared with the device with a 60% coverage channel, the device with a 100% coverage channel possesses 3520% and 8030% normalized leakage current improvement for both NFET and PFET under the bulk substrate, respectively. Compared with bulk-substrate devices, the SOI-substrate devices further significantly improve the leakage current. Due to enhanced off-state current leakages in the 100% covered bulk-substrate device, the static power demonstrates a notable improvement (about 98.1%), compared to 60% covered devices. Hence, the utilization of a 60% covered channel will result in a degradation of both device and circuit performance. The observation of GAA NS MOSFET indicates that an increase in the bottom parasitic channel coverage ratio leads to a positive impact on power consumption and leakage currents. The examination presented here is useful in the fabrication of stacked GAA NS MOSFETs.

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Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

Cited by 16 publications

References 18 publications

New structure transistors for advanced technology node CMOS ICs

New structure transistors for advanced technology node CMOS ICs

Leakage and Thermal Reliability Optimization of Stacked Nanosheet Field-Effect Transistors with SiC Layers

Effect of Parasitic Channel on DC/AC/RF Characteristics and Power Consumption of GAA Si NS MOSFETs and Circuits

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