Narrow Width and Length Dependence of SiGe and Sallow-Trench-Isolation Stress Induced Defects in 45 nm p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with Strained SiGe Source/Drain

Abstract

The effects of mechanical stress induced by both a strained SiGe source/drain (S/D) and shallow-trench-isolation (STI) on interface states in 45 nm p-type metal-oxide-semiconductor field-effect transistors (PMOSFETs) were studied in detail. An improved low gate-leakage gated-diode measurement was applied to the investigation of total induced defects. As channel width was scaled down, total defect density decreased markedly with decreasing channel length to a value less than 0.24 mm. It was opposite to the increase with decreasing channel length in conventional deep-submicron devices without SiGe S/D. The mechanism was also analyzed and proven by technology computer aided design package (T-CAD) simulations.