Nature of Electrically Induced Defects in CVD-grown Monolayer MoS2

Abstract

We find that defects are also introduced by prolonged operation of single crystal CVD-grown monolayer MoS2 FETs which hinder the overall performance. These defects result in threshold voltage instabilities, enhanced channel conductance, improved screening of charged impurity scattering sites and better thermal management in MoS2 transistors. It turns out that long-term electrical stress (LTES) results in a piezoelectric response in MoS2 which leads to permanent change in the material’s molecular configuration. This change in the molecular structure of MoS2 is, in fact, weakening of Mo-S bonds. Such a deviation from the original crystal structure results in suppressed hopping transport within the channel while increasing free electron concentration and hence reduction in channel potential without increasing sulfur vacancy concentration. It is also found that these defects result in enhanced thermal dissipation capability of MoS2 transistors. These results are particularly important from a fundamental perspective because they unveil a unique self-adaptive piezoelectric response in MoS2 against long-term high-field transport which eventually modifies its electrical and thermal transport properties. This is an entirely new property of single crystal CVD-grown monolayer MoS2 which has remained unidentified. It triggers a need to reconsider supply voltage requirements of MoS2-based CMOS circuits for low-power logic applications.

Role of Chalcogen Defect Introducing Metal-Induced Gap States and Its Implications for Metal–TMDs’ Interface Chemistry

“…Figure 7 reflects that the band structure has more trap states once the metal interacts with TMDs in the presence of the chalcogen vacancy. Thus, the chalcogen vacancy at the metal−TMD interface can play a key role in MIGS-assisted contact resistance engineering at the interface as demonstrated by Ansh et al 20 for TMDs and by Kumar et al 17 for graphene.…”

“…However, the electronegativity of the metal can also play a vital role in electron cloud sharing at the interfaces. Thus, based on the previous experimental and theoretical investigation by Ansh et al, 20 gold (Au), chromium (Cr), nickel (Ni), and palladium (Pd) metals were picked for our atomic-level investigations using DFT. Cr/Au was picked as a low-/high-work function (∼4.5/ ∼5.4 eV) and low-/high-electronegativity (∼1.66/∼2.54) metal.…”

“…The method not only helps reduce the tunnel barrier by strengthening the contact metal and TMD bonding, but it also provides a knob to change the MIGS at the interface that offers the possibility of the Fermi-level pinning at the desired energy level. Ansh et al 20,21 have demonstrated contact resistance engineering of metal−TMD interfaces using MIGS and tunnel barrier engineering with the help of chalcogen interstitial doping. Their work confirms that the discussed atomic-level orbital overlap understanding and its implications, like tunnel barrier reduction and MIGSs, can be an effective tool to reduce the contact resistance of the metal− TMD interfaces.…”

“…The method not only helps reduce the tunnel barrier by strengthening the contact metal and TMD bonding, but it also provides a knob to change the MIGS at the interface that offers the possibility of the Fermi-level pinning at the desired energy level. Ansh et al 20,21 have demonstrated contact resistance engineering of metal−TMD interfaces using…”

“…Besides, the scope of vacancy-assisted orbital overlap-based contact resistance engineering, like graphene, 17−19 is yet to be explored for TMDs at the atomic level. Ansh et al 20,21 used MIGSs and defect-induced gap states (DIGSs) as engineering tools, drastically reducing contact resistance at the TMD− metal interfaces. They have investigated the role of MIGSs and DIGSs at the Pd−TMD bulk interfaces and implemented their findings in the TMD FETs.…”