NBTI and HCI models for circuit level aging simulations in different EDA environments

Gonzalez, Fabio A. Velarde; Lange, André; Crocoll, Sonja; Jancke, Roland

doi:10.5281/zenodo.2558154

2019

DOI: 10.5281/zenodo.2558154

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NBTI and HCI models for circuit level aging simulations in different EDA environments

Fabio A. Velarde Gonzalez¹,

André Lange²,

Sonja Crocoll³

et al.

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Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits

Lange

Gonzalez

Lahbib³

et al. 2019

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)

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The degradation of integrated field effect transistors (FETs) is an increasingly critical effect for electronic systems and their product lifetimes. To allow reliability investigations during integrated circuit (IC) design already, multiple electronic design automation (EDA) vendors offer aging simulation capabilities based on SPICE simulations. So far, the bottleneck of aging simulations is the availability of corresponding degradation models that mimick the long-term behavior of FETs due to, for instance, Hot Carrier Injection (HCI) and Bias Temperature Instability (BTI). IC designers need reasonable models that support their particular EDA environment; foundries need to equally support multiple EDA environments to satisfy different customers. To define FET degradation models, subcircuits and model card adaptations are feasible approaches with individual pros and cons. We compare these approaches at example degradation models with identical direct current (DC) behavior. A simulation study with ring oscillators (ROs) shows differences in transient simulation results. By applying subcircuit models, the runtime for simulating the aged circuit worsens by 28 % compared to model card adaptations at a 1000-transistor circuit.

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Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits

Lange

Gonzalez

Lahbib³

et al. 2019

ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC)

View full text Add to dashboard Cite

show abstract

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NBTI and HCI models for circuit level aging simulations in different EDA environments

Cited by 1 publication

References 0 publications

Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits

Comparison of modeling approaches for transistor degradation: model card adaptations vs subcircuits

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