NBTI-aware statistical circuit delay assessment

Vaidyanathan, Balaji; Oates, A. S.; Xie, Yuan; Wang, Yu

doi:10.1109/isqed.2009.4810263

Cited by 14 publications

(6 citation statements)

References 11 publications

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“…As can be seen in (8) and (11) , the mean of the average difference Z n remains unchanged when compared with each X i . On the other hand, the variance of Z n is dependent on √ n. A similar derivation is carried out to estimate the resultant mean and variance for the distribution at time t, g t (f FD ).…”

Section: A Spread Reduction By Averaging Methodsmentioning

confidence: 85%

“…Undeniably, NBTI is well known to researchers and manufacturers alike as a dominant ageing mechanism in all different configurations of integrated circuits (ICs). For instance, in the post-IC manufacturing period of 7 to 10 years, accelerated ageing due to NBTI has been reported by [5] and [8] as degradation in threshold voltage up to 50 mV. Speed degradation (of 20%) follows these shifts in threshold voltage and, therefore, shows a strong correlation between NBTI prompted delay and threshold voltage shift.…”

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confidence: 99%

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Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

et al. 2020

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The ageing phenomenon of negative bias temperature instability (NBTI) continues to challenge the dynamic thermal management of modern FPGAs. Increased transistor density leads to thermal accumulation and propagates higher and non-uniform temperature variations across the FPGA. This aggravates the impact of NBTI on key PMOS transistor parameters such as threshold voltage and drain current. Where it ages the transistors, with a successive reduction in FPGA lifetime and reliability, it also challenges its security. The ingress of threshold voltage-triggered hardware Trojan, a stealthy and malicious electronic circuit, in the modern FPGA, is one such potential threat that could exploit NBTI and severely affect its performance. The development of an effective and efficient countermeasure against it is, therefore, highly critical. Accordingly, we present a comprehensive FPGA security scheme, comprising novel elements of hardware Trojan infection, detection, and mitigation, to protect FPGA applications against the hardware Trojan. Built around the threat model of a naval warship's integrated self-protection system (ISPS), we propose a threshold voltage-triggered hardware Trojan that operates in a threshold voltage region of 0.45V to 0.998V, consuming ultra-low power (10.5nW), and remaining stealthy with an area overhead as low as 1.5% for a 28 nm technology node. The hardware Trojan detection sub-scheme provides a unique lightweight threshold voltage-aware sensor with a detection sensitivity of 0.251mV/nA. With fixed and dynamic ring oscillatorbased sensor segments, the precise measurement of frequency and delay variations in response to shifts in the threshold voltage of a PMOS transistor is also proposed. Finally, the FPGA security scheme is reinforced with an online transistor dynamic scaling (OTDS) to mitigate the impact of hardware Trojan through run-time tolerant circuitry capable of identifying critical gates with worst-case drain current degradation. INDEX TERMS Ageing mechanism, field programmable gate array (FPGA), hardware Trojan, negative bias temperature instability (NBTI), propagation delay, reliability, threshold voltage. I. INTRODUCTION A modern FPGA is not merely an emulator but a hardware accelerator with heterogenous hard IP cores, such as complex memory blocks, multiple processors, and DSP blocks. Systems on chip (SoC), network on chip (NoC), and adaptive compute acceleration platform (ACAP) are the significant performance and functional enhancements of FPGAs, that have been made possible due to the continual shrinking of transistor sizes down to the scales of 10 nm and below. The performance benefits, however, are limited by power The associate editor coordinating the review of this manuscript and approving it for publication was Luis Javier Garcia Villalba. and timing closures. Similarly, the geometric structures of FPGAs with much less silicon and relatively more oxide and moulding compound complicate the heat conduction paths [1]. On the one hand, where it may deteriorate the worstcase heat dissi...

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Section: A Spread Reduction By Averaging Methodsmentioning

confidence: 85%

mentioning

confidence: 99%

Ingress of Threshold Voltage-Triggered Hardware Trojan in the Modern FPGA Fabric–Detection Methodology and Mitigation

et al. 2020

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“…They differ in the type of reliability effects considered and the type of circuits studied. For digital circuits, NBTI-aware statistical timing analysis considering process variations are proposed in (Vaidyanathan, Oates, Xie & Wang, 2009), ), (Wang et al, 2008) and (Lu et al, 2009). Authors in (Vaidyanathan, Oates, Xie & Wang, 2009) build up gate-level delay fall-out model by propagating the device parameter fall-out model due to NBTI and process variations into the gate delay model.…”

Section: State Of the Artmentioning

confidence: 99%

Lifetime Yield Optimization of Analog Circuits Considering Process Variations and Parameter Degradations

Pan¹,

Graeb²

2011

Advances in Analog Circuits

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“…The delay models are commonly based on the Sakurai's a power law MOSFET model [1], to express the transistor current, which does not take into account the prevalent effects characteristic for present nanometer technologies. Moreover, most papers do not model the joint effect of multiple aging mechanisms [12][13][14][15], and very few consider the aged signal slope [2] as wearout monitor. In [3], the authors propose a delay model considering both Time Dependent Dielectric Breakdown (TDDB) and Negative Bias Temperature Instability (NBTI).…”

Section: Introductionmentioning

confidence: 99%