Abstract-Random telegraph signal (RTS) is shown to be an intrinsic component of the shift in MOSFET threshold voltage (V th ) due to bias temperature instability (BTI). This is done by starting from a well-known model for negative BTI (NBTI), to derive the formula for RTS-induced V th shift. Based on this analysis, RTS simply contributes an offset in NBTI degradation, with an acceleration factor that is dependent on the gate voltage and temperature. This is verified by 3-dimensional (3-D) device simulations and measurements of 45nm-node bulk-Si PMOS transistors. It has an important implication for design of robust SRAM arrays in the future: design margin for RTS should not be simply added, because it is already partially accounted for within the design margin for NBTI degradation.