NBTI in (Si)Ge Channel Devices

Dangling bond defects (DBs) in silicon-passivated (1-or 3-nm thick Si cap) strained-(100)Si1-xGex (x=0.25-0.55) layers at interfaces with 1.8-nm thick HfO2 gate dielectric are studied by means of Electron Spin Resonance (ESR) spectroscopy. The results suggest a dominant contribution of Si DBs (Pb0 centers), a considerable fraction of which is located at the interface between the Si substrate crystal and the pseudomorphic Si1-xGex film. The density of Si DBs in the Ge containing samples is significantly lower than at the reference (100)Si/ HfO2 interface and decreases below the ESR detection limit (≈1x10 11 cm-2) with increasing thickness and Ge concentration in the Si1-xGex layer. However, the beneficial effect of Ge becomes less pronounced when the thickness of the Si cap is reduced to 1 nm or in the case of direct deposition of HfO2 on top of uncapped Si1-xGex. From these observations we conclude that DBs are eliminated due to in-diffusion of Ge from the Si1-xGex channel into Si, bringing the concentration of Ge to the range in which generation of Si DBs becomes energetically unfavourable, in agreement with previous observations on condensation-grown Si1-xGex layers.

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NBTI tolerance and leakage reduction using gate sizing

Lin

Syu

2014

J. Emerg. Technol. Comput. Syst.

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Leakage power is a major design constraint in deep submicron technology and below. Meanwhile, transistor degradation due to Negative Bias Temperature Instability (NBTI) has emerged as one of the main reliability concerns in nanoscale technology. Gate sizing is a widely used technique to reduce circuit leakage, and this approach has recently attracted much attention with regard to improving circuits to tolerate NBTI. However, these studies only consider timing and area constraints, and many other important issues, such as slew and max-load, are missing. In this article, we present an efficient gate sizing framework that can reduce leakage and improve circuit reliability under timing constraints. Our algorithms consider slack, slew and max-load constraints. The benchmarks are those from ISPD 2012, which feature industrial design properties, including discrete cell sizes, nonconvex cell timing models, slew dependencies and constraints, as well as large design sizes. The experimental results obtained from ISPD 2012 benchmark circuits demonstrate that our approach can meet all the constraints and tolerated NBTI degradation with a power savings of 6.54% as compared with the traditional method.

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NBTI in (Si)Ge Channel Devices

Cited by 3 publications

References 41 publications

Statistical Distribution of Defect Parameters

Statistical Distribution of Defect Parameters

Dangling bond defects in silicon-passivated strained-Si1−xGex channel layers

NBTI tolerance and leakage reduction using gate sizing

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