NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

Pugsley, Seth H.; Jestes, Jeffrey; Zhang, Huihui; Balasubramonian, Rajeev; Srinivasan, Vijayalakshmi; Buyuktosunoglu, Alper; Davis, Al; Li, Feifei

doi:10.1109/ispass.2014.6844483

Cited by 212 publications

(156 citation statements)

References 36 publications

Supporting

Mentioning

152

Contrasting

Order By: Relevance

“…al. have proposed adding general-purpose in-order cores to the base die of a stacked DRAM to run Map-Reduce workloads more efficiently [40]. For throughput-oriented computing, the TOP-PIM architecture has been proposed to add programmable GPU compute units inside stacked DRAM to achieve significant energy efficiency improvements compared to the traditional GPU architectures [41].…”

Section: Google's Tensor Processing Unitmentioning

confidence: 99%

Emerging Accelerator Platforms for Data Centers

Özdal

2018

IEEE Des. Test

View full text Add to dashboard Cite

Today's server architectures are designed considering the needs of a wide range of applications. For example, superscalar processors include complex control logic for out of order execution to extract instruction-level parallelism (ILP) from arbitrary programs. However, not all workloads utilize the features of a superscalar processor effectively. For example, a workload that exhibits a regular execution pattern (e.g. a dense linear algebra kernel) may not require the expensive ILP control logic for parallelism. Instead, it can be run on a throughput-oriented architecture with thousands of simple cores, such as a GPU, which can lead to much better performance and power efficiency. On the other hand, only a limited class of data-parallel applications can utilize the high throughputs provided by such architectures. As a matter of fact, existing CPU and GPU platforms may not be the most efficient choices for the compute patterns of a wide range of applications.For big data workloads, access to data is typically at least as important bottleneck as computation. The memory subsystems of today's CPU architectures are optimized for workloads that have reasonable data access locality. CPU cache hierarchies include different sizes of caches, which help capture different levels of access localities in different applications. However, if an application exhibits very little or no locality, the data access operations become inefficient for these architectures.As an example, let us consider graph applications that run on very large and unstructured datasets. Typically, the data of a vertex is computed/updated based on the data of its neighbors. In an unstructured graph, the neighbors of a vertex are stored in memory locations that may be far from each other. So, traversing the neighbors of a vertex may involve a random memory access per neighbor. If the graph is large enough so that it does not fit into the last level cache (LLC), each access to a neighbor's data may require a random DRAM access, which is typically hundreds of clock cycles. However, existing CPU architectures are not optimized for frequent random DRAM accesses. For example, each Intel Haswell Xeon core has 10 line-fill-buffers (LFBs), which means that each core can handle at most 10 L1 cache misses at a given time. However, an off-chip DRAM latency of hundreds of cycles requires hundreds of outstanding memory requests to be able to utilize the full DRAM bandwidth available in the system [1]. It was reported that 10 or more Xeon cores were needed for various graph applications to fully utilize the available DRAM bandwidth [2]. Furthermore, due to the low compute to memory-access ratios in graph applications, these cores are frequently stalled while waiting for data from off-chip memory. This leads to high power consumption by 10+ superscalar cores while not doing useful work. It was shown that custom architectures that target such communication patterns have the potential to improve power efficiency by a factor of 50x or more compared to the general-purpose CPU...

show abstract

Section: Google's Tensor Processing Unitmentioning

confidence: 99%

Emerging Accelerator Platforms for Data Centers

Özdal

2018

IEEE Des. Test

View full text Add to dashboard Cite

show abstract

“…Dynamic directories can reduce the exchange of network control messages, leading to energy conservation. The use of a 3D-stacked memory-logic system for MapReduce workloads is explored in [3]. Such designs involve the use of two separate specialized architectures for Map and Reduce phases.…”

Section: Related Workmentioning

confidence: 99%

“…There is great interest in designing multicore chips that are customized for emerging big-data workloads [1], [2], [3]. In this regard, energy-efficient implementations of the MapReduce framework using single chip multicore platforms can enable new discoveries in big data computing.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient MapReduce with VFI-enabled multicore platforms

Duraisamy

Kim

Choi

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

View full text Add to dashboard Cite

In an era when power constraints and data movement are proving to be significant barriers for high-end computing, multicore architectures offer a low-power and highly scalable platform suitable for both data-and compute-intensive applications. MapReduce is a popular framework to facilitate the management and development of big-data workloads. In this work, we demonstrate that by using a wireless NoC-enabled Voltage Frequency Island (VFI)-based multicore platform it is possible to enhance the energy efficiency of MapReduce implementations without paying significant execution time penalties. Our experimental results show that for the benchmarks considered, the designed VFI system can achieve an average of 33.7% energy-delay product (EDP) savings over the standard baseline non-VFI meshbased system while paying a maximum of 3.22% execution time penalty.

show abstract

“…There are also several related work demonstrating 3D-stacked DRAM and processing elements integrated together for application acceleration [8], [26], [27], and for general purpose computing [6], [10], [5], [7]. Integrating a high-performance general purpose processor underneath the DRAM raises some thermal issues, on the other hand, energy-efficient accelerators are specific to a certain application.…”

Section: Related Workmentioning

confidence: 99%

HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM

Akin

Hoe

Franchetti

2014

2014 IEEE High Performance Extreme Computing Conference (HPEC)

View full text Add to dashboard Cite

Abstract-Memory layout transformations via data reorganization are very common operations, which occur as a part of the computation or as a performance optimization in data-intensive applications. These operations require inefficient memory access patterns and roundtrip data movement through the memory hierarchy, failing to utilize the performance and energy-efficiency potentials of the memory subsystem. This paper proposes a highbandwidth and energy-efficient hardware accelerated memory layout transform (HAMLeT) system integrated within a 3D-stacked DRAM. HAMLeT uses a low-overhead hardware that exploits the existing infrastructure in the logic layer of 3D-stacked DRAMs, and does not require any changes to the DRAM layers, yet it can fully exploit the locality and parallelism within the stack by implementing efficient layout transform algorithms. We analyze matrix layout transform operations (such as matrix transpose, matrix blocking and 3D matrix rotation) and demonstrate that HAMLeT can achieve close to peak system utilization, offering up to an order of magnitude performance improvement compared to the CPU and GPU memory subsystems which does not employ HAMLeT.

show abstract

NDC: Analyzing the impact of 3D-stacked memory+logic devices on MapReduce workloads

Cited by 212 publications

References 36 publications

Emerging Accelerator Platforms for Data Centers

Emerging Accelerator Platforms for Data Centers

Energy efficient MapReduce with VFI-enabled multicore platforms

HAMLeT: Hardware accelerated memory layout transform within 3D-stacked DRAM

Contact Info

Product

Resources

About