Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory

Glova, Alvin Oliver; Akgun, Itir; Li, Shuangchen; Hu, Xing; Xie, Yuan

doi:10.23919/date.2019.8715108

Cited by 13 publications

(9 citation statements)

References 22 publications

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“…This case study aims to analyze when a workload can benefit from different core models and numbers of cores while respecting the area and power envelope of the logic layer of a 3D-stacked memory. Many prior works employ 3D-stacked memories as the substrate to implement NDP architectures [1,46]- [48,54,55,59]- [61,63]- [70,74]- [77,79,80,99,101]- [103,137,146,192,194,305,316]- [324]. However, 3D-stacked memories impose severe area and power restrictions on NDP architectures.…”

Section: Case Study 3: Impact Of Different Core Models On Ndp Architecturesmentioning

confidence: 99%

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Oliveira¹,

Gómez-Luna

Orosa

et al. 2021

IEEE Access

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Data movement between the CPU and main memory is a first-order obstacle against improving performance, scalability, and energy efficiency in modern systems. Computer systems employ a range of techniques to reduce overheads tied to data movement, spanning from traditional mechanisms (e.g., deep multi-level cache hierarchies, aggressive hardware prefetchers) to emerging techniques such as Near-Data Processing (NDP), where some computation is moved close to memory. Prior NDP works investigate the root causes of data movement bottlenecks using different profiling methodologies and tools. However, there is still a lack of understanding about the key metrics that can identify different data movement bottlenecks and their relation to traditional and emerging data movement mitigation mechanisms. Our goal is to methodically identify potential sources of data movement over a broad set of applications and to comprehensively compare traditional compute-centric data movement mitigation techniques (e.g., caching and prefetching) to more memory-centric techniques (e.g., NDP), thereby developing a rigorous understanding of the best techniques to mitigate each source of data movement. With this goal in mind, we perform the first large-scale characterization of a wide variety of applications, across a wide range of application domains, to identify fundamental program properties that lead to data movement to/from main memory. We develop the first systematic methodology to classify applications based on the sources contributing to data movement bottlenecks. From our large-scale characterization of 77K functions across 345 applications, we select 144 functions to form the first open-source benchmark suite (DAMOV) for main memory data movement studies. We select a diverse range of functions that (1) represent different types of data movement bottlenecks, and (2) come from a wide range of application domains. Using NDP as a case study, we identify new insights about the different data movement bottlenecks and use these insights to determine the most suitable data movement mitigation mechanism for a particular application. We open-source DAMOV and the complete source code for our new characterization methodology at https: //github.com/CMU-SAFARI/DAMOV.

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Section: Case Study 3: Impact Of Different Core Models On Ndp Architecturesmentioning

confidence: 99%

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

Oliveira¹,

Gómez-Luna

Orosa

et al. 2021

IEEE Access

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“…Thus, as many as n clock cycles may be necessary to complete a single addition in the ASIC implementation of SCAM [9]. Recently, [10] proposed the use of dense 3-D memories along with near-memory processing for a secure CAM search. Although the proposed framework enables high density, the energy and latency overheads of data transfers could be further reduced with CiM.…”

Section: Related Work: Cim and Hementioning

confidence: 99%

“…We compare the energy and performance of CiM-SCAM with an ASIC approach presented in [9], which demonstrates superiority in terms of search time and energy compared to CPU implementations of the same SCAM algorithm, as described in the literature [9], [10]. When comparing to the ASIC [9] implementation of SCAM, we account for data transfers and for the energy and time spent on computations.…”

Section: ) Energy and Performancementioning

confidence: 99%

“…In this context, dense memories may be useful toward scaling HE applications. For example, a near-memory processing solution based on the hybrid memory cube (HMC) was proposed to enable a more energyand area-efficient implementation for searching on homomorphically encrypted data [10]. Still, while density is an essential characteristic of memories used in HE applications, near-memory processing solutions, such as in [10], cannot reduce the number of data transfers between the memory and a processing unit.…”

Section: Introductionmentioning

confidence: 99%

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A Computing-in-Memory Engine for Searching on Homomorphically Encrypted Data

Reis

Niemier

2019

IEEE J. Explor. Solid-State Comput. Devices Circuits

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The high volumes of data stored in the cloud, coupled with growing concerns about security and privacy, have motivated research on homomorphic encryption (HE), i.e., a technique that enables computation directly on encrypted data, obviating the need for prior decryption. Recent algorithmic advances have enabled a diverse set of homomorphic operations (e.g., addition, multiplication, and division). Looking at the applications, recent work also suggests extensibility secure, homomorphically encrypted content-addressable memories [or secure content-addressable memories (SCAMs)]. Still, the large datawords that result from homomorphic data encodings (i.e., that must be stored/transferred for computation), compounded with the implicit computational complexity of HE, still impede the deployment of homomorphic computer hardware. As an alternative, computing-in-memory (CiM) architectures could significantly reduce the volume of data transfers for SCAM (and other) applications, leading to considerable energy savings and latency reduction. In this regard, we propose a CiM-compatible engine for SCAM (CiM-SCAM) and analyze the pros and cons of three different memory cells: a 6T CMOS SRAM and two memory cells based on ferroelectric field-effect transistors (FeFETs) (specifically 2T + 1FeFET and 1-FeFET designs). CiM-SCAM leverages in-place copy buffers (IPCBs), along with customized sense amplifiers that include two types of in-memory adders. Our results suggest that energy (and search time) improvements of up to 16× (3.2×) for 1-FeFET memory cells are possible, compared with an application-specific integrated circuit (ASIC) approach. Similar improvements are also possible with SRAM and 2T + 1-FeFET memory cells. For the latter, we achieve up to 13× (3.1×) of energy (speedup). INDEX TERMS Computing-in-memory (CiM), emerging technologies, ferroelectric field-effect transistors (FeFETs), homomorphic encryption (HE), secure content-addressable memory (CAM), SRAMs.

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“…While SHE enables secure and private computing in the cloud, the large size of ciphertexts (hundreds of KB) may result in low speeds due to long computation times as well as the need to constantly transfer data between memory and the CPU. New computing paradigms such as Near-Memory Processing (NMP) and Computing-in-Memory (CiM) are potential solutions for reducing the overhead of data transfers between memory and the CPU [6]- [10]. NMP reduces the energy and latency associated with memory accesses by placing processing units close to the memory.…”

Section: Introductionmentioning

confidence: 99%

Computing-in-Memory for Performance and Energy Efficient Homomorphic Encryption

Reis,

Takeshita,

Jung

et al. 2020

Preprint

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Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) -paradigms where computation is done within the memory boundariesrepresent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation.When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-toend tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPUbased HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally,our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGAbased accelerator.

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Near-Data Acceleration of Privacy-Preserving Biomarker Search with 3D-Stacked Memory

Cited by 13 publications

References 22 publications

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

DAMOV: A New Methodology and Benchmark Suite for Evaluating Data Movement Bottlenecks

A Computing-in-Memory Engine for Searching on Homomorphically Encrypted Data

Computing-in-Memory for Performance and Energy Efficient Homomorphic Encryption

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