Near-threshold CNTFET SRAM cell design with gated cell power supply

Abstract

In this paper we report an in-depth study of power supply reduction towards near-threshold for an 8-transistor CNTFET S RAM cell. Near-threshold voltage provides savings in power consumption, but has negative impact on delays, noise margin and yield. We have incorporated a removed metallic CNT approach to deal with non-semiconductor CNTs. Monte Carlo simulations have shown that with Vdd down to 0.5V, 0.72% of the cells are non-functional after removing the metallic CNTs. The power saving is over 5X, while the average delay is increased by 3.5X as compared to 0.9V Vdd. To further improve yield and performance, the gated cell power supply technique is applied which weakens the pull-up transistors during write and effectively eliminates all the write failures at near-threshold voltage level. At Vdd=0.5V, the cell with gated power supply improves write performance and write EDP by 1.5X and 2.9X compared to the non-gated cell. It also saves 70% total energy and achieves 38% lower EDP than a cell at nominal Vdd (0.9V).Index Terms-CNTFET, 8T S RAM cell, near-threshold scaling, gated power supply, removed metallic CNT tolerance.

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

“…But in Figure 4e, despite of the larger overshoots and undershoots (�2μA) during WL's rise-time under 0.33 V supply voltage, the Logic-1 voltage-level never drops below V th in read mode (Figure 4c,d), thus all CNTFETs can act properly. In this condition, Q and QN store correct values in each write process (Figure 4c), then BL and BLB sense these values in each read process (Figure 4d), however, this 6T bitcell still has some problems in 'read mode', 'leakage current' and 'power dissipations' that has already been reported in [10,12,34,36,41,49,52,57]. As observed, the current spikes in Figure 4e cause voltagereduction (discharge) during the read process in Figure 4d.…”

“…Albeit this 6T structure is conventional for typical bitcells, it suffers from leakage power during standby mode [10], worse Read SNM [34], negative impacts of nearthreshold supply voltage on R/W delays and SNM and yield [41], subthreshold leakage currents [57], etc. By applying the reported CNTFET in Ref.…”

“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”

Jump test for metallic CNTs in CNFET-based SRAM

“…Shahidipour et al [17] studied the CNT diameter variation in the CNFET-based S-RAM to minimize the noise margin and write margin. Zhang and Delgado-Frias proposed CNFET-based SRAM design operating in the near-threshold region to improve the write performance and energy-delay-product [24]. Their approach incorporated an m-CNT removal technique.…”

“…1(a), wherein CNTs are aligned in parallel to form the transistor channel. According to [24], up to 3.5× power saving can be achieved by CNFETbased SRAMs when compared to conventional MOSFET-based SRAM.…”