Nearest neighbour interconnect architecture in deep submicron FPGAs

Roopchansingh, A.; Rose, Jonathan

doi:10.1109/cicc.2002.1012766

Cited by 11 publications

(6 citation statements)

References 7 publications

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“…Recently, reference [45] proposes a bent routing pattern based on VTR to enhance the routing architecture which can achieve 11% area-delay product savings. Reference [42] proposes the nearest neighbor interconnect architecture where direct connections are used between two LBs, bypassing all the intermediate routing switches and achieves 6.4% improvement in performance. Reference [39] enhances classical FPGA architecture with direct connections between intra-and intercluster LUTs to mitigate the delay of programmable routing and achieve 2.77% improvement in the critical path delay.…”

Section: Related Workmentioning

confidence: 99%

An Optimized GIB Routing Architecture with Bent Wires for FPGA

Shi¹,

Zhou²,

Zhou³

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

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Field Programmable Gate Arrays (FPGAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on the FPGA area, delay and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), while most researches have focused on the SB architectures, such as Wilton, Universal and Disjoint SB patterns. In this paper, we propose a novel unidirectional routing architecture, general interconnection block (GIB) to improve the FPGA performance. With GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. Besides, we enhance VTR to support GIB with bent wires and develop a searching framework base on simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.

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Section: Related Workmentioning

confidence: 99%

An Optimized GIB Routing Architecture with Bent Wires for FPGA

Shi¹,

Zhou²,

Zhou³

et al. 2022

ACM Trans. Reconfigurable Technol. Syst.

View full text Add to dashboard Cite

show abstract

“…The key type of wire that is used by our optimization strategies is the Nearest Neighbour (NN) Interconnect [8]. It is a dedicated set of wires that connects horizontally adjacent CLBs.…”

Section: The Virtex-e Routing Architecturementioning

confidence: 99%

“…The routing architecture consists of four types of wires: single-length wires between neighboring CLBs, the NearestNeighbour interconnect [8] length six wires, connecting CLBs that are six rows/columns apart, and significantly longer wires.…”

Section: The Virtex-e Routing Architecturementioning

confidence: 99%

A synthesis oriented omniscient manual editor

Czajkowski

Rose

2004

Proceedings of the 2004 ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays

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The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing analysis. This distance has given rise to the field of physical synthesis, which attempts to improve logic synthesis by employing cost functions that contain placement, routing and/or timing analysis information.In this work we take this notion to an extreme that we call omniscience, in which post-routing timing analysis is provided in the context of a manual editor in which the user selects logical and physical transformations. After each incremental circuit modification, the user is informed of the circuit performance after routing and timing analysis. Since the computations involved in providing this level of information are large, we restrict the application to relatively small circuits, no larger than 1000 logic elements.Using this approach on a commercial FPGA, we propose a set of logic transformations specific to the logic and routing architecture of the Xilinx Virtex-E device. On a set of 10 circuits we have achieved an average performance improvement of 10% when both logical and physical changes are used. Another value of the editor is that it reveals new types of automatable physicalsynthesis transformations and optimization strategies that arise from architectural properties of the target device.

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“…Numerous commercial FPGAs [23,125,231] allow for direct connections between logic blocks to avoid the need to drive the interconnect fabric. The work in [165] showed that these connections, which avoid delays in traversing connection blocks and switch blocks for very near neighbor connections, can improve speed by 6.4% at a small (3.8%) area cost. In [107], an architecture which drives wires of length 5 directly between logic blocks is proposed although the specific benefits of the technique are not enumerated.…”

Section: Additional Routing Structure Improvement Approachesmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon¹,

Tessier²,

Rose³

2007

169

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field. Programming Technologies Every FPGA relies on an underlying programming technology that is used to control the programmable switches that give FPGAs their programmability. There are a number of programming technologies and their differences have a significant effect on programmable logic architecture. The approaches that have been used historically include EPROM [81], EEPROM [68, 174], flash [92], static memory [49], and anti-fuses [38, 93]. Of these approaches, only the flash, static memory and anti-fuse approaches are widely used in modern FPGAs. This survey focuses primarily on static memory-based FPGAs but, in this section, all these modern programming technologies will be reviewed to provide a more complete understanding of the advantages and disadvantages of static memory-based programming.

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Nearest neighbour interconnect architecture in deep submicron FPGAs

Cited by 11 publications

References 7 publications

An Optimized GIB Routing Architecture with Bent Wires for FPGA

An Optimized GIB Routing Architecture with Bent Wires for FPGA

A synthesis oriented omniscient manual editor

FPGA Architecture: Survey and Challenges

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