Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

Danković, Danijel; Manić, I.; Davidović, V.; Djorić-Veljković, S.; Golubović, S.; Stojadinović, N.

doi:10.1016/j.microrel.2007.07.022

Cited by 15 publications

(7 citation statements)

References 14 publications

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“…During NBT stress, under the influence of the electric field, positive charge rapidly accumulates in the oxide by capturing available holes at oxygen vacancies distributed near the silicon-silicon dioxide interface [39]:…”

Section: Nbti Mechanismsmentioning

confidence: 99%

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

Živanović,

Veljković,

Mitrović

et al. 2024

Micromachines

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This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.

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Section: Nbti Mechanismsmentioning

confidence: 99%

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

Živanović,

Veljković,

Mitrović

et al. 2024

Micromachines

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“…NBT stress-induced threshold voltage instabilities in commercial power VDMOSFETs, as well as the implications of related degradation on device lifetime have been extensively investigated in our research in the last decade [27,[42][43][44]. Although in many experiments devices have been subjected to various NBT stress (static or pulsed) and annealing conditions [9,23,25,45,46,[48][49][50][51][52], in this section a part of results obtained during static NBT stress and annealing is presented, with attention to insight into the NBTI as a result of sequential NBT stress and bias annealing steps.…”

Section: Nbt Stress Effectsmentioning

confidence: 99%

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

et al. 2018

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In this paper we provide an overview of instabilities observed in commercial power VDMOSFETs subjected to irradiation, NBT stress, and to consecutive exposure to them. The results have indicated that irradiation of previously NBT stressed devices leads to additional threshold voltage shift, while NBT stress effects in previously irradiated devices depend on the gate bias applied during irradiation and on the total dose received. This points to the importance of the order of applied stresses, indicating that for proper insight into the prediction of device behaviour not only harsh conditions, but also the order of exposure have to be considered. It has also been shown that changes in the densities of oxide trapped charge and interface traps during spontaneous recovery after each of applied stresses can be significant, thus leading to additional instability, even though the threshold voltage seems to remain stable, pointing to the need for clarifying the responsible mechanisms.

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“…As is well known, the changes in device threshold voltage during the NBT stress are attributed to the generation of oxide-trapped charge and interface traps due to stress-initiated electrochemical processes and reactions involving oxide and interface defects, holes, and various species (H • , H 2 , H + , OH, H 2 O, H 3 O + ) associated with the presence of hydrogen as a common impurity in MOS devices. [1][2][3]5,12,[44][45][46] Buildup of oxide charge under the high negative oxide field can be explained by hole trapping at near-interface oxygen vacancy defects: [42] O…”

Section: Permanent and Recoverable Components Of ∆V T ∆V T ∆V Tmentioning

confidence: 99%

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET

Danković¹,

Stojadinović²,

Prijić³

et al. 2015

Chinese Phys. B

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In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

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Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs

Cited by 15 publications

References 14 publications

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

A Reliability Investigation of VDMOS Transistors: Performance and Degradation Caused by Bias Temperature Stress

NBT stress and radiation related degradation and underlying mechanisms in power VDMOSFETs

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET

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