Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Schroder, D.K.; Babcock, J.A.

doi:10.1063/1.1567461

Cited by 940 publications

(426 citation statements)

References 81 publications

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“…It has been observed that the effect of NBTI becomes more severe because of the introduction of nitrogen into the gate dielectric which is done primarily to reduce the boron penetration from P+ poly gate into the thin oxide and also for reducing the gate leakage [5]. Criterion for the device failure is still a debatable topic, Schroder et al [6] proposed that device failure criteria is often benchmarked at v th shift of 50 mV or ΔI ds /I ds ~ 10% but still it is circuit dependent.…”

Section: Nbti Degradation Mechanismmentioning

confidence: 99%

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A Review of NBTI Degradation and its Impact on the Performance of SRAM

Dutta

Soni

Pattanaik

2016

IJMECS

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Abstract-Temporal degradation of VLSI design is a major reliability concern for highly scaled silicon IC technology. Negative Bias Temperature Instability (NBTI) in particular is a serious threat affecting the performance of both digital and analog circuits with time. This paper presents a review of NBTI degradation, its mechanism and various factors that affect the degradation caused by NBTI. Reaction Diffusion (RD) model based analytical expressions developed by various researchers are also discussed along with their features and underlying assumptions. Degradation in the Static RAM (SRAM) performance caused by NBTI is also discussed in detail along with the strategies that are employed to combat the effect of NBTI degradation in SRAM. Results of the review done for SRAM cell under NBTI degradation suggests that these design strategies are effective in improving the SRAM cell performance.

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Section: Nbti Degradation Mechanismmentioning

confidence: 99%

“…As discussed in [8] the interfacial traps density in case of H 2 only diffusion is given by- (6) with time exponent of (n = 1/6).…”

Section: H H H  (4)mentioning

confidence: 99%

A Review of NBTI Degradation and its Impact on the Performance of SRAM

Dutta

Soni

Pattanaik

2016

IJMECS

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“…On JEDEC Standard JEP122G, reliability models as Electromigration [32], Ohmic contact degradation [33] [44], NBTI [45] are generally expressed by a function of stress parameter or by a function of an electrical predictor multiplying the exponential activation energy factor.…”

Section: Reliability Mathematics and Toolsmentioning

confidence: 99%

Microelectronic reliability models for more than moore nanotechnology products

Bensoussan¹

2017

FACTA U EE

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“…NBTI occurs when PMOS transistors are negatively biased (i.e., V gs = −V dd ) at elevated temperature, causing a shift in threshold voltages. Over a long period of time, such V th shifts can potentially cause a significant increase in the delay of PMOS devices [2], and result in about 10-20% degradation in cir- 1 This work was supported by National Natural Science Foundation of China (No. 60870001, No.90207002) and TNList Cross-discipline Foundation.…”

Section: Introductionmentioning

confidence: 99%

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

Wang

Chen

Wang

et al. 2009

2009 10th International Symposium on Quality of Electronic Design

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Abstract-1 As technology scales, the aging effect caused by Negative Bias Temperature Instability (NBTI) has become a major reliability concerns for circuit designers. Consequently, we have seen a lot of research efforts on NBTI analysis and mitigation techniques. On the other hand, reducing leakage power remains to be one of the major design goals. Both NBTI-induced circuit degradation and standby leakage power have a strong dependency on the input patterns of circuits. In this paper, we propose a co-simulation flow to study NBTI-induced circuit degradation and leakage power, taking into account the different behaviors between circuit active and standby time. Based on this flow, we evaluate the efficacy of Input Vector Control (IVC) technique on mitigating circuit aging and reducing standby leakage power with experiments on benchmark circuits that are implemented in 90nm, 65nm, and 45nm technology nodes. The IVC technique is proved to be effective to mitigate NBTI-induced circuit degradation, saving up to 56% circuit performance degradation at 65nm technology node, and on average 30% circuit performance degradation across different technology nodes. Meanwhile, IVC technique can save up to 18% of the worst case leakage power. Since leakage power and NBTI-induced circuit degradation have different dependencies on the input patterns, we propose to derive Pareto sets for designers to explore trade-offs between the life-time reliability and leakage power.

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Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing

Cited by 940 publications

References 81 publications

A Review of NBTI Degradation and its Impact on the Performance of SRAM

A Review of NBTI Degradation and its Impact on the Performance of SRAM

Microelectronic reliability models for more than moore nanotechnology products

On the efficacy of input Vector Control to mitigate NBTI effects and leakage power

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