Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach

Kaushal, Shelja; Rana, Ashwani K.

doi:10.1007/s12633-021-01392-x

Cited by 14 publications

(4 citation statements)

References 31 publications

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“…Recently in 2022, a junctionless 14 nm strain-engineered NC-FinFET presented in [55], achieved I ON = 6. 5 10 4 ´and I OFF = 1.9 10 4 ´with SS = 56 mV/dec and DIBL = −66 mV/V exhibiting 12% improvement in I ON /I OFF ratio over a nominal JL-FinFET device.…”

Section: Negative Capacitance Fets-boosting Gaafets Tfets and Finfetsmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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The progress in IC miniaturization dictated by Moore’s Law has taken a leap from mere circuit integration to IoT enabled System-on-Chip (SoC) deployments. Such systems are connoted by contemporary advancements in the semiconductor industry roadmaps namely, ‘More-Moore’ and ‘More-than-Moore’ (MtM). For meaningful integration of digital and non-digital blocks, a power performance tradeoff is essential for maximum and fruitful utilization of the silicon area. Using the techniques under the MtM nomenclature allows the use of unconventional steep slope devices like Tunneling FETs, Negative Capacitance (NC) FETs, Gate-all-around FETs (GAA) and FinFETs etc., which can exhibit reasonable performance with lower supply voltages. Following the Device Technology Co-optimization (DTCO) and System Technology Co optimization (STCO) the advanced 3D heterogenous integration technologies allow sensors, analog/mixed signal and passive components to be assimilated within the same package as the CMOS blocks. Appropriate device engineering techniques like multi-gate architectures, vertical stacking transistors, compound semiconductors and alternate carrier transport phenomena are required to improve the current drive and scaling performance of advanced CMOS devices. CMOS based codesign is essential to realize new topologies for energy economical computation, sensing and information processing as the beyond CMOS steep slope devices are independently incapable of replacing conventional bulk CMOS devices. This article presents a detailed qualitative review of the various aspects of MtM beyond CMOS steep slope switches and their prospective integration technologies. For system level integration, various aspects of device performance and optimizations, related device-circuit interactions, dielectric technologies at the advance nanometer nodes have been probed into. Additionally, novel circuit topologies, synthesis algorithms and processor level performance evaluation using steep slope switches have been investigated. An exclusive compact overview for contemporary insights into integrated device-system development methodology and its performance evaluation is presented.

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Section: Negative Capacitance Fets-boosting Gaafets Tfets and Finfetsmentioning

confidence: 99%

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

Chowdhury,

Sarkar,

Mahapatra

et al. 2024

Phys. Scr.

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“…In continuation of advancement, junctionless FETs (JLFETs) could be the preferable choice over the conventional ones due to the CMOS-compatible fabrication process flow and prevention of mobility degradation from surface roughness scattering. The JLFETs alleviate the steep and shallow source-drain junction doping profile requirements, expensive ultra-rapid annealing, and thermal budget requirement of the non-planar devices [16][17][18][19][20][21]. JLFETs comprise uniform source/drain/channel doping; therefore, a higher work function is needed to completely deplete the channel, resulting in reduced I OFF .…”

Section: Introductionmentioning

confidence: 99%

“…Moreover, to improve the sensitivity characteristics, we proposed an amalgamation of negative capacitance (NC) features at the gate stack obtained using a doped HfO 2 ferroelectric (FE) layer. The NC phenomenon results in an internal voltage amplification owing to capacitance matching and offers steep subthreshold slope characteristics, which results in a lower I OFF and higher I ON /I OFF ratio [16]. All in all, we realized a novel junctionless negative capacitance (JLNC) FinFET as a hydrogen sensor and thoroughly investigated it using well-calibrated TCAD models [22].…”

Section: Introductionmentioning

confidence: 99%

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

Gandhi,

Jaisawal,

Rathore

et al. 2024

Smart Mater. Struct.

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This work demonstrates the reliability-aware analysis of the Junctionless Negative Capacitance (NC) FinFET employed as a hydrogen (H2) gas sensor. Gate stacking of the ferroelectric (FE) layer induces internal voltage amplification owing to the NC property, thus, improving the sensitivity of the baseline Junctionless FinFET. A well-calibrated TCAD model is used to investigate the sensing characteristics of the proposed FinFET-based H2 sensor by employing the Palladium (Pd) metallic gate as a sensing element. The mechanism involves the transduction of H2 gas molecules over the metal gate; due to the diffusion process, some atomic hydrogen diffuses into the metal. The H2 gas absorption at the metal surface causes a dipole layer formation at the gate and oxide interface, which changes the metal gate work function. As a result, this change in the work function can be used as a sensing parameter of the proposed gas sensor. Further, the threshold voltage and other electrical characteristics, such as output conductance, transconductance, and drain current are examined for sensitivity analysis for both NC and without NC JL FinFET at different pressure ranges, keeping the temperature constant (i.e., 300K). The device variation, i.e., Fin thickness, Fin height, doping and thickness of HfO2 ferroelectric layer, etc., on sensor sensitivity has been evaluated through extensive simulation. This paper also presents a detailed investigation of the sensor's reliability in terms of work function variation, random dopant fluctuation, trap charges, and device aging, i.e., end of a lifetime (EOL). At last, the acquired results are compared with earlier reported data, which justifies the profound significance of the proposed Junctionless Negative Capacitance (JLNC) FinFET-based H2 gas sensor.

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“…FinFET technology adds a second gate opposite the normal gate to improve controllability for low voltage operations. FinFET requires both gates to function [5]. When these gates attain equal potential, it reaches shorted gate (SG) mode.…”

Section: Introductionmentioning

confidence: 99%

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

Rao¹,

Mamidipaka²,

Raghutu³

et al. 2023

Journal of Electrical and Computer Engineering

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Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, and this trend is expected to continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set of difficulties, that results in higher leakage current (Ileakage) at lower strategy collisions. Fin field effect transistor (FinFET) is a highly effective substitute to complementary metal oxide semiconductor (CMOS) under the 45 nm variant due to advanced stability. Memory cells are significant in the large-scale computation system. SRAM is the most commonly used memory type; SRAMs are thought to utilize more than 60% of the chip area. The proposed SRAM cell is developed with FinFETs at 16 nm knot. Power, delay, power delay product (PDP), Ileakage, and stationary noise margin (SNM) are compared with traditional 6T SRAM cells. The designed cell decreases leakage power, current, and read access time. While comparing 6T SRAM and earlier low power SRAM cells, FinFET-based 10T SRAM provides significant SNM with reduced access time. The proposed 10T SRAM based on FinFET provides an 80.80% PDP reduction in write mode and a 50.65% PDP reduction in read mode compared to MOSEFET models. There is an improvement of 22.20% in terms of SNM and 25.53% in terms of Ileakage.

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Negative Capacitance Junctionless FinFET for Low Power Applications: An Innovative Approach

Cited by 14 publications

References 31 publications

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

More-than-moore steep slope devices for higher frequency switching applications: a designer’s perspective

A proof of concept for reliability aware analysis of junctionless negative capacitance FinFET-based hydrogen sensor

Design and Development of Efficient SRAM Cell Based on FinFET for Low Power Memory Applications

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