Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage

Choi, Woo Young

doi:10.3390/mi11060543

Cited by 3 publications

(4 citation statements)

References 28 publications

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“…Since the thickness of the Au electrode is 40 nm, much bigger than the L ch , it is not suitable to characterize the gap by atomic force microscopy. The linearity of I DS – V DS curves suggests that there is no direct tunneling current from the source to the drain (Figure b). − In the transfer characteristics, the leakage current (black line) of the device is less than 10 –12 A, close to the noise level (Figure c). The off-state and on-state currents of our 3 nm L ch FET are 6.53 × 10 –13 and 1.32 × 10 –7 A, respectively, so the on/off ratio is 2 × 10 5 , at the same level compared with the about 10 nm L ch device.…”

Section: Resultsmentioning

confidence: 90%

“…The I DS – V DS output curves of the Si/SiO 2 /MoS 2 /h-BN FETs with various L ch values manifest a linear characteristic (Figure d–f), indicating the Ohmic contact between the channel material and the Au electrode. Note that a small source-drain voltage between −0.5 and 0.5 V was applied during the test in order to avoid electrical breakdown and electron tunneling from the drain to the source electrode since the L ch is too small. − …”

Section: Resultsmentioning

confidence: 99%

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3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection

Wan

et al. 2023

ACS Appl. Electron. Mater.

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Further scaling down the feature size of transistors is central for the development of next-generation electronic devices. However, fabrication of transistors with channel lengths down to 5 nm has been challenging due to lithography limit and short channel effects (SCEs). Here, we demonstrate an MoS 2 -based device with the shortest 3 nm channel length among global back-gated transistors by feedback-controlled electromigration of metal interconnection. The Si/SiO 2 -back-gated model device shows on/ off ratios of up to 2 × 10 5 and exhibits a field-effect mobility of up to 33.5 cm 2 V −1 s −1 , which is, to the best of our knowledge, the highest value in the as-yet-reported same-type transistors with a sub-10 nm channel length. This good immunity of the device to SCEs is also corroborated by the COMSOL Multiphysics simulation. After replacing the thicker physical gate SiO 2 dielectric and Si electrode with the 2D hexagonal boron nitride (h-BN) and graphene monolayer, respectively, for better gate control, the field-effect mobility is pushed to 51.2 cm 2 V −1 s −1 and displays excellent switching characteristics with near-ideal subthreshold swing of 67 mV dec −1 and drain-induced barrier lowering as low as 0.378 V V −1 . This work can promote further transistor downscaling and extend Moore's law.

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Section: Resultsmentioning

confidence: 90%

Section: Resultsmentioning

confidence: 99%

3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection

Wan

et al. 2023

ACS Appl. Electron. Mater.

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“…Moreover, hybrid devices that combine the technical performance advantages of vacuum tubes with the submicron-scale integration technologies of solid-state transistors are also rapidly developing. Because electrons are transported in vacuum when they move from one electrode to another, such hybrid devices are often termed as nanoscale vacuum channel transistors (NVCTs) [6][7][8][9][10][11][12][13][14].…”

Section: Introductionmentioning

confidence: 99%

Planar nanoscale vacuum channel transistors based on resistive switching

Zhang,

Zhan

et al. 2024

Nanotechnology

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Resistance switching (RS) offers promising applications in a variety of areas. In particular, silicon oxide (SiOx) under RS can serve as electron sources in new types of miniature vacuum electron tubes. In this work, planar nanoscale vacuum channel transistors (NVCTs) with graphene electrodes and RS SiOx electron sources were developed. In each RS-NVCT, the resistance between the ground and the gate underwent high–low–high transitions, which resulted from formation and subsequent rupture of Si conducting filaments. Electrons were emitted from the post-reset Si filaments and the current received by the collector (IC) was well controlled by the gate voltage (VG). The transfer characteristics reveal that IC was quite sensitive to VG when RS occurred. With VG sweeping from 0 to −20 V, the obtained subthreshold swing (SS) of 76 mV/dec was quite close to the theoretical limit of the SS of a field effect transistor at room temperature (60 mV/dec). The largest ON/OFF ratio was of the order of 106. The output characteristics of the devices indicate that the dependence of IC on the collector voltage (VC) weakened at high VC values. These results demonstrate the application potential of RS-NVCTs as either switching devices or amplifiers.

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“…To make sure that VDD and Vth scale proportionally with transistor dimension without causing serious Ioff increase, steep SS devices are needed. Nowadays, tunneling field effect transistors (TFET), impact ionization transistors (I-FET), nano-electromechanical FETs (NEMFET), Dirac source FETs (DSFET) and negative capacitance FETs (NC-FET) [11][12][13][14][15] are proposed steep SS devices. They all have their merits but also face limitations.…”

Section: Introductionmentioning

confidence: 99%

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

Qin

Wei

et al. 2023

IEEE Access

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With transistors scaling down to 3 nm node and beyond, short channel effect (SCE) as well as power consumption dissipation present immense challenges for further scaling down of the transistor. Hence the Gate all around field effect transistor (GAA-FET) is proposed to replace the Fin field effect transistor (FinFET) in 3 nm technology node and beyond due to its better gate control over the channel with surrounding gate structure, thus providing improved SCE constraint ability. Traditional transistors suffer from the problems of "Boltzmann Tyranny" and cannot overcome the subthreshold swing (SS) limit of 60 mV/dec at room temperature. To maintain high Ion and avoid Ioff from increasing too much, supply voltage (VDD) of the conventional transistor cannot scale down proportionally with the dimension of the transistor. The concept of negative capacitance (NC) has been demonstrated to be able to obtain sub-60 mV/dec SS with the ability of amplifying the potential of the channel region without VDD increment. The novel device structure of negative capacitance gate all around field effect transistor ( NC GAA-FET) can combine both the advantages of GAA-FET and NC-FET, and is the most promising ultra-low power consumption device and promises to sustain the Moore's law further beyond what is predicted now. Whereas, according to our knowledge, there have been few review papers about NC GAA-FET till now. Herein, we summarize the recent advances of the NC GAA-FET both in simulation and experimental aspects, which we believe will bring about profound changes to the further development of NC GAA-FET devices.INDEX TERMS Negative capacitance effect, short channel effect, subthreshold swing, power consumption dissipation, negative capacitance gate all around field effect transistor.

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Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage

Cited by 3 publications

References 28 publications

3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection

3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection

Planar nanoscale vacuum channel transistors based on resistive switching

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

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Negative Capacitance Vacuum Channel Transistors for Low Operating Voltage

Cited by 3 publications

References 28 publications

3 nm Channel MoS2 Transistors by Electromigration of Metal Interconnection

3 nm Channel MoS2 Transistors by Electromigration of Metal Interconnection

Planar nanoscale vacuum channel transistors based on resistive switching

Recent Developments in Negative Capacitance Gate-All-Around Field Effect Transistors: A Review

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Product

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3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection

3 nm Channel MoS₂ Transistors by Electromigration of Metal Interconnection