Negative gate-bias instability of ZnO thin-film transistors studied by current–voltage and capacitance–voltage analyses

Abstract

Effects of negative gate-bias stress on the electrical properties of ZnO thin-film transistors (TFTs) are investigated. Under negative gate-bias stress, the ZnO TFTs exhibit higher carrier mobility, larger OFF-state current, and a negative shift in threshold voltage with no significant change in subthreshold slope. The time dependence of threshold-voltage shift on various bias stress conditions can be described by a logarithmic equation. Based on the analysis of hysteresis behaviors in current-voltage and capacitance-voltage characteristics before and after the negative gate-bias stress, it can be clarified that the threshold-voltage shift is predominantly attributed to the trapping of positive charge carriers in the defect states at the gate-dielectric/channel interface or in the dielectric during the negative gate-bias stress. V

The influence of ZnO layer thickness on the performance and electrical bias stress instability in ZnO thin film transistors

“…We observed that the shifted characteristics curves returned freely to their original positions after relaxation time of 4 hours in air at room temperature following a 10 4 s stress time. This suggests that charge trapping at or near the interface in the semiconductor is the dominant mechanism responsible for the instability [27]. It has been shown that ZnO TFT performance parameters (μ eff , V T and V On ) are affected by ZnO active layer thickness.…”