Negative Impact of Etched Si Area on Selectivity and Positive Impact of Photoelectric Current on Etched Profile in Gate Etching with Different Wafer Bias Frequencies

Abstract

The effect of wafer-bias frequency on the dummy-gate fabrication of fin-shaped field-effect transistor (Fin-FET) was investigated. The clear difference in the selectivity of polycrystalline silicon to SiO2 between 400 kHz and 13.56 MHz decreased when the etched Si area increased. On the other hand, a higher frequency increased such selectivity when Si area decreased. These results can be explained by the effect of by-product deposition. As for the etched profile, the amount of side etching was much larger at 13.56 MHz than at 400 kHz. It was reported that this phenomenon is caused by local charging. It was also suggested that the charging should be suppressed by reducing the ratio of ion saturation current to photoelectric current. Therefore, in this study, we investigated the effect of such current ratio on side etching. The result confirmed that a reduction in current ratio induced by increasing gas pressure decreases the amount of side etching.

Progress in nanoscale dry processes for fabrication of high-aspect-ratio features: How can we control critical dimension uniformity at the bottom?

“…82,83) Kamibayashi et al discussed the effect of wafer bias frequencies on etched profiles. 99) Negishi and co-workers reported that the mask edge roughness was transferred with amplification of the roughness amplitude, leading to deformed pattern profiles with profile distortion at the hole bottom. 100,101) Such profile distortion problems have always been an issue for the plasma-etching fabrication of HAR features.…”