Negative-resistance read and write schemes for STT-MRAM in 0.13&amp;#x00B5;m CMOS

Halupka, David; Huda, Safeen; Song, Won Kyung; Sheikholeslami, Ali; Tsunoda, Koji; Yoshida, Chikako; Aoki, Masaki

doi:10.1109/isscc.2010.5433943

Cited by 44 publications

(28 citation statements)

References 4 publications

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“…The average power consumption of a write-operation is mainly determined by the average pulse-width of the write-pulses. In a conventional scheme [6,10,12], every write-pulse has the same pulse-width, which is determined by the longest switching time to be accommodated. If we assume that variation of switchingtime follows Gaussian distribution, the write error-rate (ER) can be expressed as function of write-pulse width (t w ) by…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Usually reference cells are designed with two MTJs in opposite states connected in series or in parallel as shown in Fig. 3 [6,12,15]. Fig.…”

Section: Reference Cellmentioning

confidence: 99%

“…Therefore, a considerable amount of research is being directed for the development of STTMRAMs [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

“…Even when writing currents of the same magnitude are applied to the same MTJ cell, the switching of the MTJ-state occurs after different delays. In conventional write-schemes which use fixedpulse-width pulses [6,10,12], the pulse-width should be set to be longer than the longest switching-time of the cell to be accommodated [10,11]. This can be much longer than the average switching time; therefore, a significant power can be wasted by the continuation of the write-process long after the switching has already occurred.…”

Section: Introductionmentioning

confidence: 99%

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Low-Power Write-Circuit with Status-Detection for STT-MRAM

Shin

Park³

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-We report a STT-MRAM write-scheme, in which the length of the write-pulse is determined dynamically by sensing the status of MTJ cells. The proposed scheme can reduce the power consumption by eliminating unnecessary writing current after the switching has occurred. We also propose a reference cell design, which is optimized for the use in writecircuits. The performance of the proposed circuit was verified by SPICE level simulations of the circuit implemented in a 0.13 μm CMOS process.

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Section: Simulation Resultsmentioning

confidence: 99%

“…Usually reference cells are designed with two MTJs in opposite states connected in series or in parallel as shown in Fig. 3 [6,12,15]. Fig.…”

Section: Reference Cellmentioning

confidence: 99%

“…Therefore, a considerable amount of research is being directed for the development of STTMRAMs [4][5][6][7].…”

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Low-Power Write-Circuit with Status-Detection for STT-MRAM

Shin

Park³

2016

JSTS:Journal of Semiconductor Technology and Science

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“…For example, one of the well-known challenges in STT-MRAM is the high write cost due to the STT mechanism, which makes STT-MRAM prone to multi-bit write errors. A lot of techniques have been proposed, such as decreasing the thickness of barrier layer, adopting various circuit level approached or designing new architecture [8,9,10,11,12], to alleviate the issue. Nevertheless, these techniques may degrade the STT-MRAM performance and thus limit its usages in high-speed and low-power working memory applications.…”

Section: Introductionmentioning

confidence: 99%

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Liu

Zhang

et al. 2017

IEICE Electron. Express

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Non-volatile memories (NVMs), such as Magnetic RAM and Resistive RAM, have been considered as the potential working or storage memories in the next generation computer architectures, thanks to the various merits, such as non-volatility, low power and high speed etc. However, new technology brings simultaneously new challenges, e.g. reliability issue, before practical applications. Compared with conventional memories, the errors in NVMs are generally asymmetric, resulting in different failure rates for 0-1 and 1-0 bit flipping. Error correcting codes (ECCs) are common solutions for protecting memories from errors. The most widely used ECCs are the single error correction and double error detection (SEC-DED) codes. Unfortunately, they are primarily designed for correcting symmetric errors and their error correction capabilities are limited to only one bit. Regarding the failure characteristics (e.g., multi-bit and asymmetric) of NVMs, conventional SEC-DED codes are not efficiently applicable. This paper proposes an extended coset decoding scheme for NVMs. Our simulation results with a Hamming code (with Hamming distance of only three) as an example show the effectiveness of the proposed decoding scheme. The proposed decoding scheme can also be extended to other linear block codes and is rather suitable for scenarios with multi-bit asymmetric error features.

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Memory Challenges

Cagli

Perniola²

2022

Springer Handbooks

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Negative-resistance read and write schemes for STT-MRAM in 0.13µm CMOS

Cited by 44 publications

References 4 publications

Low-Power Write-Circuit with Status-Detection for STT-MRAM

Low-Power Write-Circuit with Status-Detection for STT-MRAM

Extended coset decoding scheme for multi-bit asymmetric errors in non-volatile memories

Memory Challenges

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