Negotiation-based track assignment considering local nets

Wong, Man-Pan; Liu, Wenhao; Wang, Ting-Chi

doi:10.1109/aspdac.2016.7428041

Cited by 15 publications

(12 citation statements)

References 17 publications

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“…erefore, we have w(Q) ≤ 8mα ′ . In addition, since F(j, P j ) > α ′ for every j ∈ P, according to [7] [8,9], track assignment [10], and detailed routing [11] and has been shown to be effective and efficient to improve the routing quality.…”

Section: Initial Solution Generationmentioning

confidence: 99%

“…where cost(ir, t) is the total cost of assigning track t to iroute ir, wl(ir, t) is the wire length cost, ol(ir, t) is the overlap cost, blk(ir, t) is the blocked interval cost, cp(ir, t) is the compactness cost, and C 2 , C 3 , and C 4 are the user-defined constants which are set as 0.2, 1000, and 1, respectively. e definition of wire length cost is adopted from the work [10]. Because the routing tracks may be nonuniform or even overlapping, the overlap cost of an iroute being assigned to a track is modified from the work [10], which is determined not only by the overlapping iroutes on that track but also by the overlapping iroutes on other tracks.…”

Section: Initial Trackmentioning

confidence: 99%

“…e definition of wire length cost is adopted from the work [10]. Because the routing tracks may be nonuniform or even overlapping, the overlap cost of an iroute being assigned to a track is modified from the work [10], which is determined not only by the overlapping iroutes on that track but also by the overlapping iroutes on other tracks. In addition, since some tracks may only cover a partial design, the blocked interval cost is the sum of blockage cost defined in [10] and the length of the iroute ir that is not on the tracks.…”

Section: Initial Trackmentioning

confidence: 99%

“…After the initial track assignment, there may be overlaps between the iroutes. erefore, we extend the negotiation-based track assignment in the work [10] to minimize the overlaps and wire length while keeping the relative order of the iroutes in each segment.…”

Section: Rip-up and Reassignmentmentioning

confidence: 99%

See 3 more Smart Citations

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

et al. 2021

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As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. In particular, the nonuniform routing track configuration and obstacles bring the largest difficulty for maintaining the same topology for all bus bits. In this paper, we first present a track handling technique to unify the nonuniform routing track configuration with obstacles. Then, we formulate the topology-aware single bus routing as an unsplittable flow problem (UFP), which is integrated into a negotiation-based global routing to determine the desired routing regions for each bus. A topology-aware track assignment is also presented to allocate the tracks to each segment of buses under the guidance of the global routing result. Finally, a detailed routing scheme is proposed to connect the segments of each bus. We evaluate our routing result with the benchmark suite of the 2018 CAD Contest. Compared with the top-3 state-of-the-art methods, experimental results show that our proposed algorithm achieves the best overall score regarding specified time limitations.

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Section: Initial Solution Generationmentioning

confidence: 99%

Section: Initial Trackmentioning

confidence: 99%

Section: Initial Trackmentioning

confidence: 99%

Section: Rip-up and Reassignmentmentioning

confidence: 99%

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Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

et al. 2021

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“…Reference [97] applies DPSO on track assignment problem, considering local nets, overlapped conflict, wirelength and blockages. And compared with the negotiation-based optimization algorithm [98], it achieves less overlap cost. Thus, it can be seen that applying SI techniques to track assignment problem is a wise approach.…”

Section: ) Track Assignmentmentioning

confidence: 99%

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

et al. 2020

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Routing is a complex and critical stage in the physical design of Very Large Scale Integration (VLSI), minimizing interconnect length and delay to optimize overall chip performance. With the rapid development of modern technology, VLSI routing faces enormous challenges such as large delay, high congestion, and high-power consumption. As a rising optimization method, Swarm Intelligence (SI) inspired from collective intelligence behaviors through cooperation or interaction with the environment provides effectiveness and robustness for solving NP-hard problems. Many researchers have consequently used SI techniques to solve routing-related problems in VLSI. This paper reviews the application of several SI techniques to the VLSI routing filed. Firstly, five commonly used SI techniques and related models, and three classic routing problems are described: Steiner tree construction, global routing and detailed routing. Then an overview of the current state of this field is given according to the above categories, and the survey offers informative discussions from five aspects: 1) Steiner minimum tree construction; 2) wirelength-driven routing; 3) obstacle-avoiding routing; 4) timing-driven routing; 5) power-driven routing. Finally, under three new technology models: X-architecture, multiple dynamic supply voltage and via-pillar, the future development trends are pointed as follows: 1) suggesting suitable SI techniques to specific routing problems for advanced technology models; 2) exploring new and available SI techniques that have not yet been applied to VLSI routing.

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Research on Methods for Very Large Scale Integration Track Assignment Routing

Yu,

Huang,

Ren

2024

MATEC Web of Conf.

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Routing is a crucial stage in the physical design of Very Large Scale Integration (VLSI) circuits, comprising three phases: global routing, track assignment routing, and detailed routing. With the development of VLSI circuits, scholars have proposed various track assignment routing algorithms. However, improving the efficiency of track assignment routing and optimizing conflicting design rules have become bottlenecks in track assignment routing problems. This study addresses these bottlenecks by utilizing single-level horizontal and vertical Steiner trees to extract routability information of local wire nets, resolving the adaptation issue between global routing and detailed routing. The proposed algorithm enhances routability information by an average of 16.07% across ten benchmark circuits. Additionally, a Generative Neural Network model based on Conditional Variational Autoencoder (CVAE) is employed to improve the efficiency of track assignment routing, yielding significant simulation results. Furthermore, a negotiation-based tear-and-reassign approach is utilized to address track congestion issues, resulting in an average optimization of 26.03% in overlap cost, with a tradeoff of sacrificing 6.67% of wirelength on average.

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Negotiation-based track assignment considering local nets

Cited by 15 publications

References 17 publications

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles

A Survey of Swarm Intelligence Techniques in VLSI Routing Problems

Research on Methods for Very Large Scale Integration Track Assignment Routing

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