NEMESIS: A software approach for computing in presence of soft errors

Didehban, Moslem; Shrivastava, Aviral; Lokam, Sai Ram Dheeraj

doi:10.1109/iccad.2017.8203792

Cited by 22 publications

(10 citation statements)

References 21 publications

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“…The NEMESIS technique introduced by [26] is a duplication with recovery technique. It replicates instructions and checks the results of memory write operations and branches' direction.…”

Section: A Review Of System-level Soft Error Mitigation Techniquesmentioning

confidence: 99%

Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks

Abich

Gava

Garibotti

et al. 2021

IEEE Trans. Circuits Syst. I

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Deep neural networks (DNNs) are being incorporated in resource-constrained IoT devices, which typically rely on reduced memory footprint and low-performance processors. While DNNs' precision and performance can vary and are essential, it is also vital to deploy trained models that provide high reliability at low cost. To achieve an unyielding reliability and safety level, it is imperative to provide electronic computing systems with appropriate mechanisms to tackle soft errors. This paper, therefore, investigates the relationship between soft errors and model accuracy. In this regard, an extensive soft error assessment of the MobileNet model is conducted considering precision bitwidth variations (2, 4, and 8 bits) running on an Arm Cortex-M processor. In addition, this work promotes the use of a register allocation technique (RAT) that allocates the critical DNN function/layer to a pool of specific general-purpose processor registers. Results obtained from more than 4.5 million fault injections show that RAT gives the best relative performance, memory utilization, and soft error reliability trade-offs w.r.t. a more traditional replication-based approach. Results also show that the MobileNet soft error reliability varies depending on the precision bitwidth of its convolutional layers.

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“…The NEMESIS technique introduced by [26] is a duplication with recovery technique. It replicates instructions and checks the results of memory write operations and branches' direction.…”

Section: A Review Of System-level Soft Error Mitigation Techniquesmentioning

confidence: 99%

Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks

Abich

Gava

Garibotti

et al. 2021

IEEE Trans. Circuits Syst. I

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“…S-SWIFT-R [17] is a flexible version of SWIFT that selects different register subsets from the microprocessor register file to be duplicated. NEMESIS [10] also detects soft errors at the compiler level. To reduce the detection overhead, it checks the results, rather than the operands, of instructions.…”

Section: Related Workmentioning

confidence: 99%

“…An SDC is hazardous because it corrupts the execution result of a program without any explicit behaviour. The instruction duplication mechanism [9][10][11], prediction-based mechanism [12,13], and assertion-based mechanism [14,15] are three types of mechanisms for the detection of SDC at the software level. Via the instruction duplication mechanism, instructions are duplicated and their results are compared to detect SDC.…”

Section: Introductionmentioning

confidence: 99%

F_Radish: Enhancing Silent Data Corruption Detection for Aerospace-Based Computing

Yang

Wang

2020

Electronics

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Radiation-induced soft errors degrade the reliability of aerospace-based computing. Silent data corruption (SDC) is the most dangerous and insidious type of soft error result. To detect SDC, program invariant assertions are used to harden programs. However, there exist redundant assertions in hardened programs, which impairs the detection efficiency. Benign errors are another type of soft error result. An assertion may detect benign errors, incurring unnecessary recovery overhead. The detection degree of an assertion represents the detection capability, and an assertion with a high detection degree can detect severe errors. To improve the detection efficiency and detection degree while reducing the benign detection ratio, F_Radish is proposed in the present work to screen redundant assertions in a novel way. At a program point, the detection degree and benign detection ratio are considered to evaluate the importance of the assertions in the program point. As a result, only the most important assertion remains in the program point. Moreover, the redundancy degree is considered to screen redundant assertions for neighbouring program points. Experimental results show that in comparison with the Radish approach, the detection efficiency of F_Radish is about two times greater. Moreover, F_Radish reduces the benign detection ratio and improves the detection degree. It can avoid more unnecessary recovery overheads and detect more serious SDC than can Radish.

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“…LABS also consists of an automated methodology to integrate fault tolerant structures into the speciic part of the design that needs to be protected, as deined by the hardware-based fault tolerant techniques. Similar to today's compilers, which can automatically add software-based fault tolerant techniques to target code to detect and recover from errors [15], LABS, realized as compiler passes in the FIRRTL hardware compiler framework, can automatically integrate hardware-based fault tolerant techniques into the circuit design, helping circuit designers evaluate their design defense against physical attacks readily without manual modiications.…”

Section: Introductionmentioning

confidence: 99%