NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing

Lockwood, John W.; McKeown, Nick; Watson, Gregory R.; Gibb, Glen; Hartke, Paul; Naous, Jad; Raghuraman, R.; Luo, Jianwen

doi:10.1109/mse.2007.69

Cited by 255 publications

(152 citation statements)

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“…To evaluate our design, we conducted two kinds of experiments. First, we performed black-box measurements, where we simulated loading our design onto a NetFPGA board [8], and monitored the time from when updates arrived at the inputs to when the resulting best route was advertised at the output (using the methodology given in [17]). Second, we performed microbenchmarks, where we instrumented our design with counters to determine (for each update) the amount of time it spent in each module of our design.…”

Section: Methodsmentioning

confidence: 99%

“…Moreover, implementing a new design no longer requires starting from scratch: just as software programming allows use of libraries of code, hardware description languages make reuse of code simple to do with open interfaces. Open-source implementations of hardware design libraries are increasingly made publicly available for commonly-implemented logic [7], [8]. Finally, the cost of programmable hardware, and hardware simulators, has dropped low enough for system builders, from students to commercial programmers, to prototype and experiment with their designs in realistic environments.…”

Section: ) Complicates Implementationmentioning

confidence: 99%

“…First, the FPGA may reside on a peripheral bus attached to the main processor. For example, within a conventional PC, an FPGA may reside on a network interface card reachable by the processor over a peripheral bus (e.g.,PCI) [8]. Second, the FPGA may be used as a co-processor, where an FPGA is used in a processor socket of a multiprocessor system [9].…”

Section: B Reconfiguring Hardware With Fpgasmentioning

confidence: 99%

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Better by a HAIR: hardware-amenable Internet routing

Mochizuki¹,

Kiyak²,

Keller³

et al. 2011

Computer Networks

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Abstract-Routing protocols are implemented in the form of software running on a general-purpose microprocessor. However, conventional software-based router architectures face significant scaling challenges in the presence of ever-increasing routing table growth and churn. Recent advances in programmable hardware and high-level hardware description languages provide the opportunity to implement BGP directly at the hardware layer. Hardware-based implementation allows designs to take advantage of the parallelization and customizability of the underlying hardware to improve performance. As a first step in this direction, we design and implement a hardware-based BGP architecture. To understand the challenges in doing this, we propose an architecture and logical design for the core components of BGP running as a logical circuit in an FPGA. We then enumerate sources of complexity and performance bottlenecks, and derive modifications to BGP that reduce complexity of hardware offloading. Our results based on update traces from core Internet routers indicate an order of magnitude improvement in processing time and throughput.

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Section: Methodsmentioning

confidence: 99%

Section: ) Complicates Implementationmentioning

confidence: 99%

Section: B Reconfiguring Hardware With Fpgasmentioning

confidence: 99%

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Better by a HAIR: hardware-amenable Internet routing

Mochizuki¹,

Kiyak²,

Keller³

et al. 2011

Computer Networks

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“…In the RR, the two SRAMs use the same clock as used by the core logic FPGA processor for writing and reading data, to ensure that transmit queues could transmit data with little or no delay between packets [24]. An inbuilt register sets the operating frequency of the core logic FPGA to either 125 MHz or 62.5 MHz.…”

Section: Frequency-scaled Routermentioning

confidence: 99%

Greening the NetFPGA Reference Router

et al. 2016

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Abstract:Energy efficiency is an important criterion in the design of next generation networks for both economic and environmental concerns. This paper presents an energy-efficient router that is able to dynamically adapt its routing capability in response to real-time traffic load, achieving energy proportional routing. The NetFPGA reference router, which operates at one of two frequencies (125 MHz or 62.5 MHz), requires a board reset to switch frequencies. We have modified the reference router to allow dynamic switching among five operating frequencies. Experiments with real traces indicate that, compared to the reference router, a 10% power reduction can be achieved through dynamic frequency scaling. When the router is further modified to support green traffic engineering and Ethernet port shut-down, power consumption can be reduced by 46% while maintaining the required quality of service. This allows the router to meet the instantaneous performance requirements while minimizing power dissipation. Similar results can be expected when these general power-saving principles are applied in future commercial routers.

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“…Popular research projects for FPGA-based networking are NetFPGA [2] and DynaCORE [3]. In contrast to these often packet-oriented approaches, our own research has always been aiming at higher-level Internet (e.g., TCP, UDP) and application protocol communication.…”

Section: A Related Workmentioning

confidence: 99%

A Scalable Multi-FPGA Platform for Complex Networking Applications

Mühlbach

Koch

2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Ballooning traffic volumes and increasing linkspeeds require ever high compute power to perform complex real-time processing of network packets. FPGAs have already been successfully employed in the past to accelerate network infrastructure-operations at these line-speed processing rates. However, much of the prior work concentrated on single-FPGA platforms. To this end, we have studied how to extend an architecture for 10G application-level network processing into a scalable multi-device system. We present a ring-based approach, of which a quad-FPGA implementation will be evaluated on the BEEcube BEE3 computing platform.

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NetFPGA--An Open Platform for Gigabit-Rate Network Switching and Routing

Cited by 255 publications

References 1 publication

Better by a HAIR: hardware-amenable Internet routing

Better by a HAIR: hardware-amenable Internet routing

Greening the NetFPGA Reference Router

A Scalable Multi-FPGA Platform for Complex Networking Applications

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